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authorvljn <vljn@91177308-0d34-0410-b5e6-96231b3b80d8>2013-02-14 16:55:01 +0000
committerTom Stellard <thomas.stellard@amd.com>2013-02-19 14:57:48 +0000
commit8c26cae042d75c8aa0a6d7f6de2c9823b1928ca5 (patch)
tree9e53e541988725c0b31d4161b11e9e56bfdfe298
parentaa29d9fcd83c1e4cbdf2ad40763dbe7c9df640e1 (diff)
R600: Do not fold modifier/litterals in vector inst
This fixes a couple of regressions on (probably not just) cayman NOTE: This is a candidate for the Mesa stable branch. Reviewed-by: Tom Stellard <thomas.stellard at amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175180 91177308-0d34-0410-b5e6-96231b3b80d8 (cherry picked from commit a0a54acc145853cfab62a54de076b92914c85501)
-rw-r--r--lib/Target/R600/AMDILISelDAGToDAG.cpp7
1 files changed, 5 insertions, 2 deletions
diff --git a/lib/Target/R600/AMDILISelDAGToDAG.cpp b/lib/Target/R600/AMDILISelDAGToDAG.cpp
index a88e8c7fc64..b125ba87ed1 100644
--- a/lib/Target/R600/AMDILISelDAGToDAG.cpp
+++ b/lib/Target/R600/AMDILISelDAGToDAG.cpp
@@ -218,7 +218,9 @@ SDNode *AMDGPUDAGToDAGISel::Select(SDNode *N) {
continue;
}
} else {
- if (!TII->isALUInstr(Use->getMachineOpcode())) {
+ if (!TII->isALUInstr(Use->getMachineOpcode()) ||
+ (TII->get(Use->getMachineOpcode()).TSFlags &
+ R600_InstFlag::VECTOR)) {
continue;
}
@@ -261,7 +263,8 @@ SDNode *AMDGPUDAGToDAGISel::Select(SDNode *N) {
if (ST.device()->getGeneration() <= AMDGPUDeviceInfo::HD6XXX) {
const R600InstrInfo *TII =
static_cast<const R600InstrInfo*>(TM.getInstrInfo());
- if (Result && Result->isMachineOpcode()
+ if (Result && Result->isMachineOpcode() &&
+ !(TII->get(Result->getMachineOpcode()).TSFlags & R600_InstFlag::VECTOR)
&& TII->isALUInstr(Result->getMachineOpcode())) {
// Fold FNEG/FABS/CONST_ADDRESS
// TODO: Isel can generate multiple MachineInst, we need to recursively