diff options
| author | ckoenig <ckoenig@91177308-0d34-0410-b5e6-96231b3b80d8> | 2013-02-16 11:28:07 +0000 |
|---|---|---|
| committer | Tom Stellard <thomas.stellard@amd.com> | 2013-02-19 15:02:03 +0000 |
| commit | 2ea2009d4f897e755e2f0bb9fe7757ddd5dd0f60 (patch) | |
| tree | 6b0934ea9ee1c200c0135a36a03e191d1c396c32 | |
| parent | 0d8755f2c3a58c457980a22f27f852870def39d0 (diff) | |
R600/SI: fix VOPC encoding v2
Previously it only worked because of coincident.
v2: fix 64bit versions, use 0x80 (inline 0) instead of SGPR0
for the unused SRC2
This is a candidate for the stable branch.
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175352 91177308-0d34-0410-b5e6-96231b3b80d8
(cherry picked from commit e2bd6eecf85510fbee0f071665125651a36b5cae)
| -rw-r--r-- | lib/Target/R600/SIInstrFormats.td | 53 |
1 files changed, 16 insertions, 37 deletions
diff --git a/lib/Target/R600/SIInstrFormats.td b/lib/Target/R600/SIInstrFormats.td index 70401152c7a..bd31bc18463 100644 --- a/lib/Target/R600/SIInstrFormats.td +++ b/lib/Target/R600/SIInstrFormats.td @@ -21,26 +21,12 @@ // //===----------------------------------------------------------------------===// -class VOP3b_2IN <bits<9> op, string opName, RegisterClass dstClass, - RegisterClass src0Class, RegisterClass src1Class, - list<dag> pattern> - : VOP3b <op, (outs dstClass:$vdst), - (ins src0Class:$src0, src1Class:$src1, InstFlag:$src2, InstFlag:$sdst, - InstFlag:$omod, InstFlag:$neg), - opName, pattern ->; - - -class VOP3_1_32 <bits<9> op, string opName, list<dag> pattern> - : VOP3b_2IN <op, opName, SReg_1, AllReg_32, VReg_32, pattern>; - class VOP3_32 <bits<9> op, string opName, list<dag> pattern> : VOP3 <op, (outs VReg_32:$dst), (ins AllReg_32:$src0, VReg_32:$src1, VReg_32:$src2, i32imm:$src3, i32imm:$src4, i32imm:$src5, i32imm:$src6), opName, pattern>; class VOP3_64 <bits<9> op, string opName, list<dag> pattern> : VOP3 <op, (outs VReg_64:$dst), (ins AllReg_64:$src0, VReg_64:$src1, VReg_64:$src2, i32imm:$src3, i32imm:$src4, i32imm:$src5, i32imm:$src6), opName, pattern>; - class SOP1_32 <bits<8> op, string opName, list<dag> pattern> : SOP1 <op, (outs SReg_32:$dst), (ins SReg_32:$src0), opName, pattern>; @@ -109,34 +95,27 @@ class SOPK_32 <bits<5> op, string opName, list<dag> pattern> class SOPK_64 <bits<5> op, string opName, list<dag> pattern> : SOPK <op, (outs SReg_64:$dst), (ins i16imm:$src0), opName, pattern>; -class VOPC_Helper <bits<8> op, RegisterClass vrc, RegisterClass arc, - string opName, list<dag> pattern> : - VOPC < - op, (ins arc:$src0, vrc:$src1), opName, pattern - >; - -multiclass VOPC_32 <bits<9> op, string opName, list<dag> pattern> { - - def _e32 : VOPC_Helper < - {op{7}, op{6}, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}}, - VReg_32, AllReg_32, opName, pattern - >; +multiclass VOPC_Helper <bits<8> op, RegisterClass vrc, RegisterClass arc, + string opName, list<dag> pattern> { - def _e64 : VOP3_1_32 < - op, + def _e32 : VOPC <op, (ins arc:$src0, vrc:$src1), opName, pattern>; + def _e64 : VOP3 < + {0, op{7}, op{6}, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}}, + (outs SReg_1:$dst), + (ins arc:$src0, vrc:$src1, + InstFlag:$abs, InstFlag:$clamp, + InstFlag:$omod, InstFlag:$neg), opName, pattern - >; + > { + let SRC2 = 0x80; + } } -multiclass VOPC_64 <bits<8> op, string opName, list<dag> pattern> { +multiclass VOPC_32 <bits<8> op, string opName, list<dag> pattern> + : VOPC_Helper <op, VReg_32, AllReg_32, opName, pattern>; - def _e32 : VOPC_Helper <op, VReg_64, AllReg_64, opName, pattern>; - - def _e64 : VOP3_64 < - {0, op{7}, op{6}, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}}, - opName, [] - >; -} +multiclass VOPC_64 <bits<8> op, string opName, list<dag> pattern> + : VOPC_Helper <op, VReg_64, AllReg_64, opName, pattern>; class SOPC_32 <bits<7> op, string opName, list<dag> pattern> : SOPC <op, (outs SCCReg:$dst), (ins SReg_32:$src0, SReg_32:$src1), opName, pattern>; |