diff options
author | Tom Stellard <thomas.stellard@amd.com> | 2012-07-16 14:17:19 +0000 |
---|---|---|
committer | Tom Stellard <thomas.stellard@amd.com> | 2012-08-02 21:00:49 +0000 |
commit | 98bc164cee8bb12c6f0a161ec8111b3901051e53 (patch) | |
tree | 9c2192b7092c896776e33d53100c0e5b81cb9098 | |
parent | 68e560762e39af35e9e83b09e8428c3081bb7582 (diff) |
test/CodeGen/R600: Add some basic tests v7r600-master
-rw-r--r-- | test/CodeGen/R600/fadd.ll | 16 | ||||
-rw-r--r-- | test/CodeGen/R600/fmul.ll | 16 | ||||
-rw-r--r-- | test/CodeGen/R600/fsub.ll | 16 | ||||
-rw-r--r-- | test/CodeGen/R600/lit.local.cfg | 13 | ||||
-rw-r--r-- | test/CodeGen/R600/llvm.AMDGPU.cos.ll | 16 | ||||
-rw-r--r-- | test/CodeGen/R600/llvm.AMDGPU.floor.ll | 16 | ||||
-rw-r--r-- | test/CodeGen/R600/llvm.AMDGPU.mul.ll | 17 | ||||
-rw-r--r-- | test/CodeGen/R600/llvm.AMDGPU.pow.ll | 19 | ||||
-rw-r--r-- | test/CodeGen/R600/llvm.AMDGPU.rcp.ll | 16 | ||||
-rw-r--r-- | test/CodeGen/R600/llvm.AMDGPU.sin.ll | 16 | ||||
-rw-r--r-- | test/CodeGen/R600/llvm.AMDGPU.trunc.ll | 16 | ||||
-rw-r--r-- | test/CodeGen/R600/llvm.AMDIL.fabs..ll | 16 | ||||
-rw-r--r-- | test/CodeGen/R600/llvm.AMDIL.max..ll | 17 | ||||
-rw-r--r-- | test/CodeGen/R600/llvm.AMDIL.min..ll | 17 |
14 files changed, 227 insertions, 0 deletions
diff --git a/test/CodeGen/R600/fadd.ll b/test/CodeGen/R600/fadd.ll new file mode 100644 index 00000000000..3d3d32ba789 --- /dev/null +++ b/test/CodeGen/R600/fadd.ll @@ -0,0 +1,16 @@ +;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s + +; CHECK: ADD + +define void @test() { + %r0 = call float @llvm.R600.load.input(i32 0) + %r1 = call float @llvm.R600.load.input(i32 1) + %r2 = fadd float %r0, %r1 + call void @llvm.AMDGPU.store.output(float %r2, i32 0) + ret void +} + +declare float @llvm.R600.load.input(i32) readnone + +declare void @llvm.AMDGPU.store.output(float, i32) + diff --git a/test/CodeGen/R600/fmul.ll b/test/CodeGen/R600/fmul.ll new file mode 100644 index 00000000000..b59c5780505 --- /dev/null +++ b/test/CodeGen/R600/fmul.ll @@ -0,0 +1,16 @@ +;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s + +; CHECK: MUL + +define void @test() { + %r0 = call float @llvm.R600.load.input(i32 0) + %r1 = call float @llvm.R600.load.input(i32 1) + %r2 = fmul float %r0, %r1 + call void @llvm.AMDGPU.store.output(float %r2, i32 0) + ret void +} + +declare float @llvm.R600.load.input(i32) readnone + +declare void @llvm.AMDGPU.store.output(float, i32) + diff --git a/test/CodeGen/R600/fsub.ll b/test/CodeGen/R600/fsub.ll new file mode 100644 index 00000000000..bb819ce50c9 --- /dev/null +++ b/test/CodeGen/R600/fsub.ll @@ -0,0 +1,16 @@ +;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s + +; CHECK: ADD + +define void @test() { + %r0 = call float @llvm.R600.load.input(i32 0) + %r1 = call float @llvm.R600.load.input(i32 1) + %r2 = fsub float %r0, %r1 + call void @llvm.AMDGPU.store.output(float %r2, i32 0) + ret void +} + +declare float @llvm.R600.load.input(i32) readnone + +declare void @llvm.AMDGPU.store.output(float, i32) + diff --git a/test/CodeGen/R600/lit.local.cfg b/test/CodeGen/R600/lit.local.cfg new file mode 100644 index 00000000000..79fc2ba362f --- /dev/null +++ b/test/CodeGen/R600/lit.local.cfg @@ -0,0 +1,13 @@ +config.suffixes = ['.ll', '.c', '.cpp'] + +def getRoot(config): + if not config.parent: + return config + return getRoot(config.parent) + +root = getRoot(config) + +targets = set(root.targets_to_build.split()) +if not 'AMDGPU' in targets: + config.unsupported = True + diff --git a/test/CodeGen/R600/llvm.AMDGPU.cos.ll b/test/CodeGen/R600/llvm.AMDGPU.cos.ll new file mode 100644 index 00000000000..d12b8ea2e7e --- /dev/null +++ b/test/CodeGen/R600/llvm.AMDGPU.cos.ll @@ -0,0 +1,16 @@ +;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s + +;CHECK: COS + +define void @test() { + %r0 = call float @llvm.R600.load.input(i32 0) + %r1 = call float @llvm.AMDGPU.cos( float %r0) + call void @llvm.AMDGPU.store.output(float %r1, i32 0) + ret void +} + +declare float @llvm.R600.load.input(i32) readnone + +declare void @llvm.AMDGPU.store.output(float, i32) + +declare float @llvm.AMDGPU.cos(float ) readnone diff --git a/test/CodeGen/R600/llvm.AMDGPU.floor.ll b/test/CodeGen/R600/llvm.AMDGPU.floor.ll new file mode 100644 index 00000000000..3a4640c5838 --- /dev/null +++ b/test/CodeGen/R600/llvm.AMDGPU.floor.ll @@ -0,0 +1,16 @@ +;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s + +;CHECK: FLOOR + +define void @test() { + %r0 = call float @llvm.R600.load.input(i32 0) + %r1 = call float @llvm.AMDGPU.floor( float %r0) + call void @llvm.AMDGPU.store.output(float %r1, i32 0) + ret void +} + +declare float @llvm.R600.load.input(i32) readnone + +declare void @llvm.AMDGPU.store.output(float, i32) + +declare float @llvm.AMDGPU.floor(float ) readnone diff --git a/test/CodeGen/R600/llvm.AMDGPU.mul.ll b/test/CodeGen/R600/llvm.AMDGPU.mul.ll new file mode 100644 index 00000000000..2f1eecc05dd --- /dev/null +++ b/test/CodeGen/R600/llvm.AMDGPU.mul.ll @@ -0,0 +1,17 @@ +;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s + +;CHECK: MUL + +define void @test() { + %r0 = call float @llvm.R600.load.input(i32 0) + %r1 = call float @llvm.R600.load.input(i32 1) + %r2 = call float @llvm.AMDGPU.mul( float %r0, float %r1) + call void @llvm.AMDGPU.store.output(float %r2, i32 0) + ret void +} + +declare float @llvm.R600.load.input(i32) readnone + +declare void @llvm.AMDGPU.store.output(float, i32) + +declare float @llvm.AMDGPU.mul(float ,float ) readnone diff --git a/test/CodeGen/R600/llvm.AMDGPU.pow.ll b/test/CodeGen/R600/llvm.AMDGPU.pow.ll new file mode 100644 index 00000000000..edc7972c2e3 --- /dev/null +++ b/test/CodeGen/R600/llvm.AMDGPU.pow.ll @@ -0,0 +1,19 @@ +;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s + +;CHECK: LOG_IEEE +;CHECK-NEXT: MUL NON-IEEE +;CHECK-NEXT: EXP_IEE + +define void @test() { + %r0 = call float @llvm.R600.load.input(i32 0) + %r1 = call float @llvm.R600.load.input(i32 1) + %r2 = call float @llvm.AMDGPU.pow( float %r0, float %r1) + call void @llvm.AMDGPU.store.output(float %r2, i32 0) + ret void +} + +declare float @llvm.R600.load.input(i32) readnone + +declare void @llvm.AMDGPU.store.output(float, i32) + +declare float @llvm.AMDGPU.pow(float ,float ) readnone diff --git a/test/CodeGen/R600/llvm.AMDGPU.rcp.ll b/test/CodeGen/R600/llvm.AMDGPU.rcp.ll new file mode 100644 index 00000000000..681a0fb26bf --- /dev/null +++ b/test/CodeGen/R600/llvm.AMDGPU.rcp.ll @@ -0,0 +1,16 @@ +;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s + +;CHECK: RECIP_IEEE + +define void @test() { + %r0 = call float @llvm.R600.load.input(i32 0) + %r1 = call float @llvm.AMDGPU.rcp( float %r0) + call void @llvm.AMDGPU.store.output(float %r1, i32 0) + ret void +} + +declare float @llvm.R600.load.input(i32) readnone + +declare void @llvm.AMDGPU.store.output(float, i32) + +declare float @llvm.AMDGPU.rcp(float ) readnone diff --git a/test/CodeGen/R600/llvm.AMDGPU.sin.ll b/test/CodeGen/R600/llvm.AMDGPU.sin.ll new file mode 100644 index 00000000000..e465964f0bd --- /dev/null +++ b/test/CodeGen/R600/llvm.AMDGPU.sin.ll @@ -0,0 +1,16 @@ +;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s + +;CHECK: SIN + +define void @test() { + %r0 = call float @llvm.R600.load.input(i32 0) + %r1 = call float @llvm.AMDGPU.sin( float %r0) + call void @llvm.AMDGPU.store.output(float %r1, i32 0) + ret void +} + +declare float @llvm.R600.load.input(i32) readnone + +declare void @llvm.AMDGPU.store.output(float, i32) + +declare float @llvm.AMDGPU.sin(float ) readnone diff --git a/test/CodeGen/R600/llvm.AMDGPU.trunc.ll b/test/CodeGen/R600/llvm.AMDGPU.trunc.ll new file mode 100644 index 00000000000..4ce78cc8be4 --- /dev/null +++ b/test/CodeGen/R600/llvm.AMDGPU.trunc.ll @@ -0,0 +1,16 @@ +;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s + +;CHECK: TRUNC + +define void @test() { + %r0 = call float @llvm.R600.load.input(i32 0) + %r1 = call float @llvm.AMDGPU.trunc( float %r0) + call void @llvm.AMDGPU.store.output(float %r1, i32 0) + ret void +} + +declare float @llvm.R600.load.input(i32) readnone + +declare void @llvm.AMDGPU.store.output(float, i32) + +declare float @llvm.AMDGPU.trunc(float ) readnone diff --git a/test/CodeGen/R600/llvm.AMDIL.fabs..ll b/test/CodeGen/R600/llvm.AMDIL.fabs..ll new file mode 100644 index 00000000000..9cb5e488205 --- /dev/null +++ b/test/CodeGen/R600/llvm.AMDIL.fabs..ll @@ -0,0 +1,16 @@ +;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s + +;CHECK: MOV + +define void @test() { + %r0 = call float @llvm.R600.load.input(i32 0) + %r1 = call float @llvm.AMDIL.fabs.( float %r0) + call void @llvm.AMDGPU.store.output(float %r1, i32 0) + ret void +} + +declare float @llvm.R600.load.input(i32) readnone + +declare void @llvm.AMDGPU.store.output(float, i32) + +declare float @llvm.AMDIL.fabs.(float ) readnone diff --git a/test/CodeGen/R600/llvm.AMDIL.max..ll b/test/CodeGen/R600/llvm.AMDIL.max..ll new file mode 100644 index 00000000000..12ce5bee140 --- /dev/null +++ b/test/CodeGen/R600/llvm.AMDIL.max..ll @@ -0,0 +1,17 @@ +;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s + +;CHECK: MAX + +define void @test() { + %r0 = call float @llvm.R600.load.input(i32 0) + %r1 = call float @llvm.R600.load.input(i32 1) + %r2 = call float @llvm.AMDIL.max.( float %r0, float %r1) + call void @llvm.AMDGPU.store.output(float %r2, i32 0) + ret void +} + +declare float @llvm.R600.load.input(i32) readnone + +declare void @llvm.AMDGPU.store.output(float, i32) + +declare float @llvm.AMDIL.max.(float ,float ) readnone diff --git a/test/CodeGen/R600/llvm.AMDIL.min..ll b/test/CodeGen/R600/llvm.AMDIL.min..ll new file mode 100644 index 00000000000..8d8d45c47e5 --- /dev/null +++ b/test/CodeGen/R600/llvm.AMDIL.min..ll @@ -0,0 +1,17 @@ +;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s + +;CHECK: MIN + +define void @test() { + %r0 = call float @llvm.R600.load.input(i32 0) + %r1 = call float @llvm.R600.load.input(i32 1) + %r2 = call float @llvm.AMDIL.min.( float %r0, float %r1) + call void @llvm.AMDGPU.store.output(float %r2, i32 0) + ret void +} + +declare float @llvm.R600.load.input(i32) readnone + +declare void @llvm.AMDGPU.store.output(float, i32) + +declare float @llvm.AMDIL.min.(float ,float ) readnone |