diff options
| author | Topi Pohjolainen <topi.pohjolainen@intel.com> | 2018-09-26 06:21:00 -0400 |
|---|---|---|
| committer | Topi Pohjolainen <topi.pohjolainen@intel.com> | 2018-10-29 14:43:47 +0200 |
| commit | e9cec8942322e6207f2648c8ff78210061ffae97 (patch) | |
| tree | 876cdb1653dfbb6939e3b444e553a86b78b9c3f2 | |
| parent | 9e56ffb0b487162de57100b0393ba188e60149d5 (diff) | |
i965/icl: Disable prefetching of sampler state entriesjenkins
In the same spirit as commit a5889d70f2074201ceaeac4f96a9a0c0b1f68a31
"i965/icl: Disable binding table prefetching". Fixes some 110+
intermittent piglit failures with tex-miplevel-selection variants.
There looks to be even hardware documentation backing this
telling we should do this at kernel level:
Gen11.2LP-GT1_JSL 1606682166 AUTOCLONE: AUTOCLONE:
Incorrect TDL's SSP address shift in SARB for 16:6 & 18:8 modes.
Disable the Sampler state prefetch functionality in the SARB by
programming 0xB000[30] to '1'. This is to be done at boot time and
the feature must remain disabled permanently.
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
| -rw-r--r-- | src/mesa/drivers/dri/i965/genX_state_upload.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/mesa/drivers/dri/i965/genX_state_upload.c b/src/mesa/drivers/dri/i965/genX_state_upload.c index 740cb0c4d2..348cb914c6 100644 --- a/src/mesa/drivers/dri/i965/genX_state_upload.c +++ b/src/mesa/drivers/dri/i965/genX_state_upload.c @@ -3977,8 +3977,8 @@ genX(upload_ps)(struct brw_context *brw) */ ps.VectorMaskEnable = GEN_GEN >= 8; - ps.SamplerCount = - DIV_ROUND_UP(CLAMP(stage_state->sampler_count, 0, 16), 4); + ps.SamplerCount = GEN_GEN == 11 ? + 0 : DIV_ROUND_UP(CLAMP(stage_state->sampler_count, 0, 16), 4); /* BRW_NEW_FS_PROG_DATA */ /* Gen 11 workarounds table #2056 WABTPPrefetchDisable suggests to disable |