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AgeCommit message (Expand)AuthorFilesLines
2018-01-11nouveau: Support fence FDsnouveau-sync-fdThierry Reding6-8/+73
2018-01-11radv: reset semaphores & fences on sync_file export.Bas Nieuwenhuizen1-0/+16
2018-01-11intel: Add more Coffee Lake PCI IDsAnuj Phogat1-1/+9
2018-01-11Revert "Revert "i965/fs: Use align1 mode on ternary instructions on Gen10+""Matt Turner1-4/+8
2018-01-11i965/fs: Add/use functions to convert to 3src_align1 vstride/hstrideMatt Turner1-28/+41
2018-01-11anv: Make sure state on primary is correct after CmdExecuteCommandsAlex Smith1-0/+9
2018-01-11svga: simplify failure code in emit_rss_vgpu9()Brian Paul1-17/+12
2018-01-11svga: remove unused fail parameter to EMIT_RS(), EMIT_RS_FLOAT()Brian Paul1-57/+57
2018-01-11svga: add assertion in svga_queue_rs()Brian Paul1-0/+1
2018-01-11svga: whitespace/formatting fixes in svga_state_rss.cBrian Paul1-79/+75
2018-01-11anv: Import mako templates only during execution of anv_extensionsAndres Gomez1-5/+5
2018-01-11glsl: cleanup shader_cache header guardTapani Pälli1-3/+3
2018-01-11anv: fix maxDescriptorSet* limitsSamuel Iglesias Gonsálvez1-5/+5
2018-01-11ac: add load_patch_vertices_in() to the abiTimothy Arceri3-7/+26
2018-01-11ac/nir: Sanitize location_frac for local variables.Bas Nieuwenhuizen1-0/+1
2018-01-10tgsi: include struct definitions for tgsi_build declarationsRob Herring1-5/+1
2018-01-10swr: Handle indirect indices in GSGeorge Kyriazis1-8/+39
2018-01-10amd/common: use ac_build_buffer_load() for emitting UBO loadsSamuel Pitoiset1-14/+3
2018-01-10amd/common: import get_{load,store}_intr_attribs() from RadeonSISamuel Pitoiset3-31/+25
2018-01-10dri_util: remove ALLOW_RGB10_CONFIGS option (v2)Marek Olšák2-5/+2
2018-01-10swr/rast: switch win32 jit format to COFFTim Rowley1-2/+2
2018-01-10swr/rast: don't use 32-bit gathers for elements < 32-bits in sizeTim Rowley1-1/+60
2018-01-10swr/rast: autogenerate named structs instead of literal structsTim Rowley1-8/+15
2018-01-10swr/rast: SIMD16 fetch shader jitter cleanupTim Rowley1-720/+368
2018-01-10swr/rast: shuffle header files for msvc pre-compiled header usageTim Rowley10-88/+143
2018-01-10swr/rast: SIMD16 builder - cleanup naming (simd2 -> simd16)Tim Rowley5-233/+239
2018-01-10glsl/linker: Safely generate mask of possible locationsIan Romanick1-4/+5
2018-01-10glsl/linker: Mark no locations as invalid instead of marking all locationsIan Romanick1-1/+1
2018-01-10glsl: Don't handle visit_stop in several ::accept methodsIan Romanick1-3/+6
2018-01-10glsl: Remove unnecessary assignments to typeIan Romanick1-4/+0
2018-01-10nir: Silence unused parameter warningsIan Romanick1-2/+2
2018-01-10radv: Remove some typos.Bas Nieuwenhuizen2-4/+4
2018-01-10radv: Implement VK_EXT_discard_rectangles.Bas Nieuwenhuizen5-6/+110
2018-01-10radv: Add mapping between dynamic state mask and external enum.Bas Nieuwenhuizen3-38/+79
2018-01-10amd/common: bump the number of available user SGPRS to 32 on GFX9Samuel Pitoiset1-1/+3
2018-01-10radv: remove radv_pipeline_layout::push_constant_stages fieldSamuel Pitoiset2-3/+0
2018-01-10amd/common: do not rely on the pipeline for the push constants logicSamuel Pitoiset3-9/+9
2018-01-10radv/gfx9: calculate the number of ES VGPRs for merged shadersSamuel Pitoiset1-3/+10
2018-01-10radv/gfx9: enable LDS for GS only if the ES type is TESSamuel Pitoiset1-1/+2
2018-01-10amd/common: determine the ES type (VS or TES) for the GS on GFX9Samuel Pitoiset2-0/+9
2018-01-10i965/nir: lower TES PatchVerticesIn to a constant when a TCS is presentIago Toral Quiroga1-4/+22
2018-01-10glsl: remove Lower{TCS,TES}PatchVerticesInIago Toral Quiroga4-31/+4
2018-01-10i965: lower gl_PatchVerticesIn to a uniformIago Toral Quiroga1-0/+8
2018-01-10i965/nir: add a helper to lower gl_PatchVerticesIn to a uniformIago Toral Quiroga2-0/+27
2018-01-10r600: don't emit tes samplers/views when tes isn't activeRoland Scheidegger2-0/+19
2018-01-10r600: increase number of UBOs to 15Roland Scheidegger3-22/+37
2018-01-10r600: use GET_BUFFER_RESINFO vtx fetch on eg instead of setting up constsRoland Scheidegger4-58/+50
2018-01-10r600: increase number of ubos by one to 14Roland Scheidegger4-4/+9
2018-01-10r600: set up constants needed for txq for buffers and cube maps with tesRoland Scheidegger1-0/+16
2018-01-10r600: don't emit reloc for ring buffer out into the blueRoland Scheidegger2-8/+6
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