diff options
| author | Thierry Reding <treding@nvidia.com> | 2014-04-16 09:06:55 +0200 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2014-06-04 12:09:29 +0200 |
| commit | b1a754ee8cea741c905a2c9fb31f0e5d7af22a94 (patch) | |
| tree | 09d102e501ff2b610da831f0244906b9ffaeb346 | |
| parent | 4b5113181dee99e523a51e60f60d1528e1d2c112 (diff) | |
WIP: clk: tegra: Add 297 MHz and 148.5 MHz frequencies for pll_d2
Signed-off-by: Thierry Reding <treding@nvidia.com>
| -rw-r--r-- | drivers/clk/tegra/clk-tegra124.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/clk/tegra/clk-tegra124.c b/drivers/clk/tegra/clk-tegra124.c index 80efe51fdcd..2f74b413557 100644 --- a/drivers/clk/tegra/clk-tegra124.c +++ b/drivers/clk/tegra/clk-tegra124.c @@ -618,6 +618,8 @@ static struct tegra_clk_pll_params pll_d_params = { }; static struct tegra_clk_pll_freq_table tegra124_pll_d2_freq_table[] = { + { 12000000, 297000000, 99, 1, 4}, + { 12000000, 148500000, 99, 1, 8}, { 12000000, 594000000, 99, 1, 2}, { 13000000, 594000000, 91, 1, 2}, /* actual: 591.5 MHz */ { 16800000, 594000000, 71, 1, 2}, /* actual: 596.4 MHz */ |