diff options
| author | Thierry Reding <treding@nvidia.com> | 2014-04-04 12:24:58 +0200 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2014-06-04 09:30:48 +0200 |
| commit | 650c649e6bc7c2d6d37dff1d5dcdc16b9dddc74f (patch) | |
| tree | bbaff9fa78192a836cfdfcdb823fe06159281621 | |
| parent | 248c83e4a110a26c8ab31c332895b21ff9b776cf (diff) | |
PCI: tegra: Make sure the PCIe PLL is really reset
Depending on the prior state of the controller, the PLL reset may not be
pulsed. Clear the register bit and set it after a small delay to ensure
that the PLL is really reset.
Signed-off-by: Eric Yuen <eyuen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
| -rw-r--r-- | drivers/pci/host/pci-tegra.c | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c index 86891da477d..06e89ca4ae2 100644 --- a/drivers/pci/host/pci-tegra.c +++ b/drivers/pci/host/pci-tegra.c @@ -856,6 +856,13 @@ static int tegra_pcie_enable_controller(struct tegra_pcie *pcie) value |= PADS_PLL_CTL_REFCLK_INTERNAL_CML | soc->tx_ref_sel; pads_writel(pcie, value, soc->pads_pll_ctl); + /* reset PLL */ + value = pads_readl(pcie, soc->pads_pll_ctl); + value &= ~PADS_PLL_CTL_RST_B4SM; + pads_writel(pcie, value, soc->pads_pll_ctl); + + usleep_range(20, 100); + /* take PLL out of reset */ value = pads_readl(pcie, soc->pads_pll_ctl); value |= PADS_PLL_CTL_RST_B4SM; |