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| author | Thierry Reding <treding@nvidia.com> | 2014-04-04 07:37:13 +0200 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2014-06-04 12:09:30 +0200 |
| commit | 03aec943db56f083452bca78d11bd966875d2389 (patch) | |
| tree | 70ffcd6635fc89d45fdca1f3f99038376d789081 | |
| parent | 45768352505aa0f019d9365c71a6dde794bdd7c7 (diff) | |
ARM: tegra: tegra124: Add XUSB pad controller
The device tree node in the SoC file contains only the resources (such
as registers, resets, ...) but none of the lane assignment information
since that's board specific and belongs in the board file.
Signed-off-by: Thierry Reding <treding@nvidia.com>
| -rw-r--r-- | arch/arm/boot/dts/tegra124.dtsi | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi index 9a51dfa295b..307d90a3d05 100644 --- a/arch/arm/boot/dts/tegra124.dtsi +++ b/arch/arm/boot/dts/tegra124.dtsi @@ -458,6 +458,17 @@ clock-names = "pclk", "clk32k_in"; }; + padctl@0,7009f000 { + compatible = "nvidia,tegra124-xusb-padctl"; + reg = <0x0 0x7009f000 0x0 0x1000>; + resets = <&tegra_car 142>; + reset-names = "padctl"; + + #address-cells = <0>; + #size-cells = <0>; + #phy-cells = <1>; + }; + sdhci@0,700b0000 { compatible = "nvidia,tegra124-sdhci"; reg = <0x0 0x700b0000 0x0 0x200>; |