diff options
Diffstat (limited to 'radeontool.c')
| -rw-r--r-- | radeontool.c | 61 |
1 files changed, 43 insertions, 18 deletions
diff --git a/radeontool.c b/radeontool.c index d6009d9..1f3f9e4 100644 --- a/radeontool.c +++ b/radeontool.c @@ -182,31 +182,49 @@ uint8_t get_vga_crtc_reg(int crtc, int reg) return retval; } +void set_crtc_owner(int crtc) +{ + int offset; + if (crtc==0) + offset = NV_PCIO0_OFFSET; + else + offset = NV_PCIO0_OFFSET + 0x2000; + + radeon_set8(offset+CRTC_INDEX, "CRTC", NV_VGA_CRTCX_OWNER); + radeon_set8(offset+CRTC_DATA, "CRTC", crtc ? 0x3 : 0x0); + +} + int dump_vga_regs(int crtc) { int i; + set_crtc_owner(crtc); + for (i = 0; i<26; i+=4) printf("CRTC%2d %02X\t%02X %02X %02X %02X\n", crtc, i, get_vga_crtc_reg(crtc, i), get_vga_crtc_reg(crtc, i+1), get_vga_crtc_reg(crtc, i+2), get_vga_crtc_reg(crtc, i+3)); #define SHOW_VGA_CRTC_REG(r) printf("%s%d\t%02x\n", #r, crtc, get_vga_crtc_reg(crtc, r)) - SHOW_VGA_CRTC_REG(NV_VGA_CRTCX_CURCTL0); - SHOW_VGA_CRTC_REG(NV_VGA_CRTCX_CURCTL1); - SHOW_VGA_CRTC_REG(NV_VGA_CRTCX_CURCTL2); - SHOW_VGA_CRTC_REG(NV_VGA_CRTCX_INTERLACE); SHOW_VGA_CRTC_REG(NV_VGA_CRTCX_REPAINT0); SHOW_VGA_CRTC_REG(NV_VGA_CRTCX_REPAINT1); SHOW_VGA_CRTC_REG(NV_VGA_CRTCX_FIFO0); SHOW_VGA_CRTC_REG(NV_VGA_CRTCX_FIFO1); - SHOW_VGA_CRTC_REG(NV_VGA_CRTCX_OWNER); - SHOW_VGA_CRTC_REG(NV_VGA_CRTCX_EXTRA); + SHOW_VGA_CRTC_REG(NV_VGA_CRTCX_LOCK); + SHOW_VGA_CRTC_REG(NV_VGA_CRTCX_FIFO_LWM); + SHOW_VGA_CRTC_REG(NV_VGA_CRTCX_BUFFER); SHOW_VGA_CRTC_REG(NV_VGA_CRTCX_LSR); SHOW_VGA_CRTC_REG(NV_VGA_CRTCX_PIXEL); SHOW_VGA_CRTC_REG(NV_VGA_CRTCX_HEB); - SHOW_VGA_CRTC_REG(NV_VGA_CRTCX_FIFO_LWM); + SHOW_VGA_CRTC_REG(NV_VGA_CRTCX_CURCTL0); + SHOW_VGA_CRTC_REG(NV_VGA_CRTCX_CURCTL1); + SHOW_VGA_CRTC_REG(NV_VGA_CRTCX_CURCTL2); + SHOW_VGA_CRTC_REG(NV_VGA_CRTCX_LCD); + SHOW_VGA_CRTC_REG(NV_VGA_CRTCX_INTERLACE); + SHOW_VGA_CRTC_REG(NV_VGA_CRTCX_EXTRA); + SHOW_VGA_CRTC_REG(NV_VGA_CRTCX_OWNER); + SHOW_VGA_CRTC_REG(NV_VGA_CRTCX_SWAPPING); SHOW_VGA_CRTC_REG(NV_VGA_CRTCX_FIFO_LWM_NV30); - SHOW_VGA_CRTC_REG(NV_VGA_CRTCX_BUFFER); SHOW_VGA_CRTC_REG(NV_VGA_CRTCX_FP_HTIMING); SHOW_VGA_CRTC_REG(NV_VGA_CRTCX_FP_VTIMING); @@ -237,6 +255,8 @@ void radeon_cmd_regs(void) SHOW_CRTC1_REG(NV_CRTC_0830); SHOW_CRTC1_REG(NV_CRTC_0834); +#define SHOW_RAMDAC0_REG(r) do { printf("%s0\t%08x\n", #r, radeon_get32(NV_PRAMDAC0_OFFSET+r, #r)); } while(0) + #define SHOW_RAMDAC_REG(r) do { printf("%s0\t%08x\n", #r, radeon_get32(NV_PRAMDAC0_OFFSET+r, #r)); \ printf("%s1\t%08x\n", #r, radeon_get32(NV_PRAMDAC1_OFFSET+r, #r)); \ } while(0) @@ -247,19 +267,24 @@ void radeon_cmd_regs(void) SHOW_RAMDAC_REG(NV_RAMDAC_CURSOR_DATA_HI); SHOW_RAMDAC_REG(NV_RAMDAC_OUTPUT); + SHOW_RAMDAC_REG(NV_RAMDAC_FP_VDISP_END); + SHOW_RAMDAC_REG(NV_RAMDAC_FP_VTOTAL); + SHOW_RAMDAC_REG(NV_RAMDAC_FP_VCRTC); + SHOW_RAMDAC_REG(NV_RAMDAC_FP_DITHER); + SHOW_RAMDAC_REG(NV_RAMDAC_FP_TEST_CONTROL); SHOW_RAMDAC_REG(NV_RAMDAC_FP_CONTROL); SHOW_RAMDAC_REG(NV_RAMDAC_FP_DEBUG_0); SHOW_RAMDAC_REG(NV_RAMDAC_GENERAL_CONTROL); - SHOW_RAMDAC_REG(NV_RAMDAC_NVPLL); - SHOW_RAMDAC_REG(NV_RAMDAC_MPLL); - SHOW_RAMDAC_REG(NV_RAMDAC_VPLL); - SHOW_RAMDAC_REG(NV_RAMDAC_PLL_SELECT); - SHOW_RAMDAC_REG(NV_RAMDAC_VPLL2); - - SHOW_RAMDAC_REG(NV_RAMDAC_NVPLL_B); - SHOW_RAMDAC_REG(NV_RAMDAC_MPLL_B); - SHOW_RAMDAC_REG(NV_RAMDAC_VPLL_B); - SHOW_RAMDAC_REG(NV_RAMDAC_VPLL2_B); + SHOW_RAMDAC0_REG(NV_RAMDAC_NVPLL); + SHOW_RAMDAC0_REG(NV_RAMDAC_MPLL); + SHOW_RAMDAC0_REG(NV_RAMDAC_VPLL); + SHOW_RAMDAC0_REG(NV_RAMDAC_PLL_SELECT); + SHOW_RAMDAC0_REG(NV_RAMDAC_VPLL2); + + SHOW_RAMDAC0_REG(NV_RAMDAC_NVPLL_B); + SHOW_RAMDAC0_REG(NV_RAMDAC_MPLL_B); + SHOW_RAMDAC0_REG(NV_RAMDAC_VPLL_B); + SHOW_RAMDAC0_REG(NV_RAMDAC_VPLL2_B); dump_vga_regs(0); dump_vga_regs(1); |