Import new reg defines, drop some regs from default list, add others

Also some warning and output formatting fixes

1 files changed, 98 insertions, 106 deletions

diff --git a/radeontool.c b/radeontool.c
index aba5918..11dd366 100644
--- a/radeontool.c
+++ b/radeontool.c
@@ -24,7 +24,7 @@
 #include <fnmatch.h>
 #include <stdint.h>
 
-#include "nouveau_reg.h"
+#include "nvreg.h"
 
 int debug=0;
 int skip;
@@ -174,9 +174,9 @@ uint8_t get_vga_crtc_reg(int crtc, int reg)
   int offset;
   uint8_t retval;
   if (crtc==0)
-    offset = NV_PCIO0_OFFSET;
+    offset = NV_PRMCIO0_OFFSET;
   else
-    offset = NV_PCIO0_OFFSET + 0x2000;
+    offset = NV_PRMCIO1_OFFSET;
 
   radeon_set8(offset+CRTC_INDEX, "CRTC", reg);
   retval = radeon_get8(offset+CRTC_DATA, "CRTC") & 0xff;
@@ -188,9 +188,9 @@ void set_vga_crtc_reg(int crtc, int reg, uint8_t val)
 {
   int offset;
   if (crtc==0)
-    offset = NV_PCIO0_OFFSET;
+    offset = NV_PRMCIO0_OFFSET;
   else
-    offset = NV_PCIO0_OFFSET + 0x2000;
+    offset = NV_PRMCIO1_OFFSET;
 
   radeon_set8(offset+CRTC_INDEX, "CRTC", reg);
   radeon_set8(offset+CRTC_DATA, "CRTC", val);
@@ -198,35 +198,24 @@ void set_vga_crtc_reg(int crtc, int reg, uint8_t val)
 
 uint32_t get_tmds_index_reg(int index, int reg)
 {
-  uint32_t idx_reg;
+  uint32_t offset = 0;
   uint32_t retval;
 
-  if (index == 0)
-	idx_reg = NV_RAMDAC_FP_TMDS_DATA;
-  else
-	idx_reg = NV_RAMDAC_FP_TMDS_OTHER;
+  if (index)
+	offset = NV_PRAMDAC0_SIZE;
 
-  radeon_set32(NV_PRAMDAC0_OFFSET + idx_reg, "FPTMDS", 0x10000 | reg);
-  retval = radeon_get32(NV_PRAMDAC0_OFFSET + idx_reg + 4, "FPTMDS");
+  radeon_set32(NV_PRAMDAC_FP_TMDS_CONTROL + offset, "FPTMDS", 0x10000 | reg);
+  retval = radeon_get32(NV_PRAMDAC_FP_TMDS_DATA + offset, "FPTMDS");
   return retval;
 }
 
 void set_crtc_owner(int crtc)
 {
-  int offset;
-  if (crtc==0)
-    offset = NV_PCIO0_OFFSET;
-  else
-    offset = NV_PCIO0_OFFSET + 0x2000;
-
-  radeon_set8(offset+CRTC_INDEX, "CRTC", NV_VGA_CRTCX_OWNER);
-  radeon_set8(offset+CRTC_DATA, "CRTC", crtc ? 0x3 : 0x0);
-
+  radeon_set8(NV_PRMCIO_CRX__COLOR, "CRTC", NV_CIO_CRE_44);
+  radeon_set8(NV_PRMCIO_CR__COLOR, "CRTC", crtc ? 0x3 : 0x0);
 }
 
-
-
-int dump_vga_regs(int crtc)
+void dump_vga_regs(int crtc)
 {
   int i;
 
@@ -236,31 +225,29 @@ int dump_vga_regs(int crtc)
     printf("CRTC%2d %02X\t%02X %02X %02X %02X\n", crtc, i, get_vga_crtc_reg(crtc, i),
 	   get_vga_crtc_reg(crtc, i+1), get_vga_crtc_reg(crtc, i+2), get_vga_crtc_reg(crtc, i+3));
 
-#define SHOW_VGA_CRTC_REG(r) printf("%s%d\t%02x\n", #r, crtc, get_vga_crtc_reg(crtc, r))
-  SHOW_VGA_CRTC_REG(NV_VGA_CRTCX_REPAINT0);
-  SHOW_VGA_CRTC_REG(NV_VGA_CRTCX_REPAINT1);
-  SHOW_VGA_CRTC_REG(NV_VGA_CRTCX_FIFO0);
-  SHOW_VGA_CRTC_REG(NV_VGA_CRTCX_FIFO1);
-  SHOW_VGA_CRTC_REG(NV_VGA_CRTCX_LOCK);
-  SHOW_VGA_CRTC_REG(NV_VGA_CRTCX_FIFO_LWM);
-  SHOW_VGA_CRTC_REG(NV_VGA_CRTCX_BUFFER);
-  SHOW_VGA_CRTC_REG(NV_VGA_CRTCX_LSR);
-  SHOW_VGA_CRTC_REG(NV_VGA_CRTCX_PIXEL);
-  SHOW_VGA_CRTC_REG(NV_VGA_CRTCX_HEB);
-  SHOW_VGA_CRTC_REG(NV_VGA_CRTCX_CURCTL0);
-  SHOW_VGA_CRTC_REG(NV_VGA_CRTCX_CURCTL1);
-  SHOW_VGA_CRTC_REG(NV_VGA_CRTCX_CURCTL2);
-  SHOW_VGA_CRTC_REG(NV_VGA_CRTCX_LCD);
-  SHOW_VGA_CRTC_REG(NV_VGA_CRTCX_INTERLACE);
-  SHOW_VGA_CRTC_REG(NV_VGA_CRTCX_EXTRA);
-  SHOW_VGA_CRTC_REG(NV_VGA_CRTCX_OWNER);
-  SHOW_VGA_CRTC_REG(NV_VGA_CRTCX_SWAPPING);
-  SHOW_VGA_CRTC_REG(NV_VGA_CRTCX_FIFO_LWM_NV30);
-  
-  SHOW_VGA_CRTC_REG(NV_VGA_CRTCX_FP_HTIMING);
-  SHOW_VGA_CRTC_REG(NV_VGA_CRTCX_FP_VTIMING);
-  SHOW_VGA_CRTC_REG(NV_VGA_CRTCX_UNK35);
-  SHOW_VGA_CRTC_REG(NV_VGA_CRTCX_UNK58);
+#define SHOW_VGA_CRTC_REG(r) printf("%s-%s\t%02x\n", #r, crtc ? "HB" : "HA", get_vga_crtc_reg(crtc, r))
+  SHOW_VGA_CRTC_REG(NV_CIO_CRE_RPC0_INDEX);
+  SHOW_VGA_CRTC_REG(NV_CIO_CRE_RPC1_INDEX);
+  SHOW_VGA_CRTC_REG(NV_CIO_CRE_FF_INDEX);
+  SHOW_VGA_CRTC_REG(NV_CIO_CRE_ENH_INDEX);
+  SHOW_VGA_CRTC_REG(NV_CIO_SR_LOCK_INDEX);
+  SHOW_VGA_CRTC_REG(NV_CIO_CRE_FFLWM__INDEX);
+  SHOW_VGA_CRTC_REG(NV_CIO_CRE_21);
+  SHOW_VGA_CRTC_REG(NV_CIO_CRE_LSR_INDEX);
+  SHOW_VGA_CRTC_REG(NV_CIO_CRE_PIXEL_INDEX);
+  SHOW_VGA_CRTC_REG(NV_CIO_CRE_HEB__INDEX);
+  SHOW_VGA_CRTC_REG(NV_CIO_CRE_HCUR_ADDR0_INDEX);
+  SHOW_VGA_CRTC_REG(NV_CIO_CRE_HCUR_ADDR1_INDEX);
+  SHOW_VGA_CRTC_REG(NV_CIO_CRE_HCUR_ADDR2_INDEX);
+  SHOW_VGA_CRTC_REG(NV_CIO_CRE_LCD__INDEX);
+  SHOW_VGA_CRTC_REG(NV_CIO_CRE_ILACE__INDEX);
+  SHOW_VGA_CRTC_REG(NV_CIO_CRE_EBR_INDEX);
+  SHOW_VGA_CRTC_REG(NV_CIO_CRE_44);
+  SHOW_VGA_CRTC_REG(NV_CIO_CRE_RCR);
+  SHOW_VGA_CRTC_REG(NV_CIO_CRE_47);
+  SHOW_VGA_CRTC_REG(NV_CIO_CRE_53);
+  SHOW_VGA_CRTC_REG(NV_CIO_CRE_54);
+  SHOW_VGA_CRTC_REG(NV_CIO_CRE_59);
 }
 
 void dump_tmds_regs(int index)
@@ -275,68 +262,74 @@ void radeon_cmd_regs(void)
 {
 	#define SHOW_REG(r) printf("%s\t%08x\n", #r, radeon_get32(r, #r))
 
-  SHOW_REG(NV_PFIFO_RAMHT);
-  SHOW_REG(NV_PFIFO_RAMRO);
-  SHOW_REG(NV_PFIFO_RAMFC);
-  SHOW_REG(NV40_PFIFO_RAMFC);
-  
-#define SHOW_CRTC_REG(r) do { printf("%08X: %s0\t%08x\n", NV_PCRTC0_OFFSET+r, #r, radeon_get32(NV_PCRTC0_OFFSET+r, #r)); \
-			      printf("%08X: %s1\t%08x\n", NV_PCRTC1_OFFSET+r, #r, radeon_get32(NV_PCRTC1_OFFSET+r, #r)); \
+SHOW_REG(NV_PMC_BOOT_0);
+SHOW_REG(NV_PMC_ENABLE);
+
+SHOW_REG(NV_PBUS_DEBUG_1);
+
+SHOW_REG(NV_PFB_CSTATUS);
+
+SHOW_REG(NV_PEXTDEV_BOOT_0);
+
+#define SHOW_CRTC_REG(r) do { printf("%08X: %s-HA\t%08x\n", r, #r, radeon_get32(r, #r)); \
+			      printf("%08X: %s-HB\t%08x\n", 0x2000+r, #r, radeon_get32(0x2000+r, #r)); \
 			} while(0)
 
-  SHOW_CRTC_REG(NV_CRTC_START);
-  SHOW_CRTC_REG(NV_CRTC_CURSOR_CONFIG);
-  SHOW_CRTC_REG(NV_CRTC_HEAD_CONFIG);
-  SHOW_CRTC_REG(NV_CRTC_081C);
-  SHOW_CRTC_REG(NV_CRTC_0830);
-  SHOW_CRTC_REG(NV_CRTC_0834);
+  SHOW_CRTC_REG(NV_PCRTC_START);
+  SHOW_CRTC_REG(NV_PCRTC_CURSOR_CONFIG);
+  SHOW_CRTC_REG(NV_PCRTC_830);
+  SHOW_CRTC_REG(NV_PCRTC_834);
+  SHOW_CRTC_REG(NV_PCRTC_ENGINE_CTRL);
 
-#define SHOW_RAMDAC0_REG(r) do { printf("%08X: %s0\t%08x\n", NV_PRAMDAC0_OFFSET+r, #r, radeon_get32(NV_PRAMDAC0_OFFSET+r, #r)); } while(0)
+#define SHOW_RAMDAC0_REG(r) do { printf("%08X: %s\t%08x\n", r, #r, radeon_get32(r, #r)); } while(0)
 
-#define SHOW_RAMDAC_REG(r) do { printf("%08X: %s0\t%08x\n", NV_PRAMDAC0_OFFSET+r, #r, radeon_get32(NV_PRAMDAC0_OFFSET+r, #r)); \
-				printf("%08X: %s1\t%08x\n", NV_PRAMDAC1_OFFSET+r, #r, radeon_get32(NV_PRAMDAC1_OFFSET+r, #r)); \
+#define SHOW_RAMDAC_REG(r) do { printf("%08X: %s-HA\t%08x\n", r, #r, radeon_get32(r, #r)); \
+				printf("%08X: %s-HB\t%08x\n", 0x2000+r, #r, radeon_get32(0x2000+r, #r)); \
 } while(0)
 
-  SHOW_RAMDAC_REG(NV_RAMDAC_CURSOR_POS);
-  SHOW_RAMDAC_REG(NV_RAMDAC_CURSOR_CTRL);
-  SHOW_RAMDAC_REG(NV_RAMDAC_CURSOR_DATA_LO);
-  SHOW_RAMDAC_REG(NV_RAMDAC_CURSOR_DATA_HI);
-  SHOW_RAMDAC_REG(NV_RAMDAC_OUTPUT);
-
-  SHOW_RAMDAC_REG(NV_RAMDAC_FP_VDISP_END);
-  SHOW_RAMDAC_REG(NV_RAMDAC_FP_VTOTAL);
-  SHOW_RAMDAC_REG(NV_RAMDAC_FP_VCRTC);
-  SHOW_RAMDAC_REG(NV_RAMDAC_FP_VSYNC_START);
-  SHOW_RAMDAC_REG(NV_RAMDAC_FP_VSYNC_END);
-  SHOW_RAMDAC_REG(NV_RAMDAC_FP_VVALID_START);
-  SHOW_RAMDAC_REG(NV_RAMDAC_FP_VVALID_END);
-  SHOW_RAMDAC_REG(NV_RAMDAC_FP_HDISP_END);
-  SHOW_RAMDAC_REG(NV_RAMDAC_FP_HTOTAL);
-  SHOW_RAMDAC_REG(NV_RAMDAC_FP_HCRTC);
-  SHOW_RAMDAC_REG(NV_RAMDAC_FP_HSYNC_START);
-  SHOW_RAMDAC_REG(NV_RAMDAC_FP_HSYNC_END);
-  SHOW_RAMDAC_REG(NV_RAMDAC_FP_HVALID_START);
-  SHOW_RAMDAC_REG(NV_RAMDAC_FP_HVALID_END);
-  SHOW_RAMDAC_REG(NV_RAMDAC_FP_DITHER);
-  SHOW_RAMDAC_REG(NV_RAMDAC_FP_TEST_CONTROL);
-  SHOW_RAMDAC_REG(NV_RAMDAC_FP_CONTROL);
-  SHOW_RAMDAC_REG(NV_RAMDAC_FP_DEBUG_0);
-  SHOW_RAMDAC_REG(NV_RAMDAC_GENERAL_CONTROL);
-  SHOW_RAMDAC_REG(NV_RAMDAC_FP_TMDS_DATA);
-  SHOW_RAMDAC_REG(NV_RAMDAC_FP_TMDS_LVDS);
-  SHOW_RAMDAC_REG(NV_RAMDAC_FP_TMDS_OTHER);
-  SHOW_RAMDAC_REG(NV_RAMDAC_FP_TMDS_OTHER2);
-  SHOW_RAMDAC0_REG(NV_RAMDAC_NVPLL);
-  SHOW_RAMDAC0_REG(NV_RAMDAC_MPLL);
-  SHOW_RAMDAC0_REG(NV_RAMDAC_VPLL);
-  SHOW_RAMDAC0_REG(NV_RAMDAC_PLL_SELECT);
+  SHOW_RAMDAC0_REG(NV_PRAMDAC_NVPLL_COEFF);
+  SHOW_RAMDAC0_REG(NV_PRAMDAC_MPLL_COEFF);
+  SHOW_RAMDAC0_REG(NV_PRAMDAC_VPLL_COEFF);
+  SHOW_RAMDAC0_REG(NV_PRAMDAC_PLL_COEFF_SELECT);
   SHOW_RAMDAC0_REG(NV_RAMDAC_VPLL2);
-  SHOW_RAMDAC0_REG(NV_RAMDAC_SEL_CLK);
+  SHOW_RAMDAC0_REG(NV_PRAMDAC_SEL_CLK);
 
   SHOW_RAMDAC0_REG(NV_RAMDAC_NVPLL_B);
   SHOW_RAMDAC0_REG(NV_RAMDAC_MPLL_B);
   SHOW_RAMDAC0_REG(NV_RAMDAC_VPLL_B);
   SHOW_RAMDAC0_REG(NV_RAMDAC_VPLL2_B);
+  SHOW_RAMDAC0_REG(NV_PRAMDAC_580);
+
+  SHOW_RAMDAC_REG(NV_PRAMDAC_DACCLK);
+  SHOW_RAMDAC_REG(0x680594);
+ 
+  SHOW_RAMDAC_REG(NV_PRAMDAC_GENERAL_CONTROL);
+
+  SHOW_RAMDAC_REG(NV_PRAMDAC_FP_VDISPLAY_END);
+  SHOW_RAMDAC_REG(NV_PRAMDAC_FP_VTOTAL);
+  SHOW_RAMDAC_REG(NV_PRAMDAC_FP_VCRTC);
+  SHOW_RAMDAC_REG(NV_PRAMDAC_FP_VSYNC_START);
+  SHOW_RAMDAC_REG(NV_PRAMDAC_FP_VSYNC_END);
+  SHOW_RAMDAC_REG(NV_PRAMDAC_FP_VVALID_START);
+  SHOW_RAMDAC_REG(NV_PRAMDAC_FP_VVALID_END);
+  SHOW_RAMDAC_REG(NV_PRAMDAC_FP_HDISPLAY_END);
+  SHOW_RAMDAC_REG(NV_PRAMDAC_FP_HTOTAL);
+  SHOW_RAMDAC_REG(NV_PRAMDAC_FP_HCRTC);
+  SHOW_RAMDAC_REG(NV_PRAMDAC_FP_HSYNC_START);
+  SHOW_RAMDAC_REG(NV_PRAMDAC_FP_HSYNC_END);
+  SHOW_RAMDAC_REG(NV_PRAMDAC_FP_HVALID_START);
+  SHOW_RAMDAC_REG(NV_PRAMDAC_FP_HVALID_END);
+
+  SHOW_RAMDAC_REG(NV_RAMDAC_FP_DITHER);
+
+  SHOW_RAMDAC_REG(NV_PRAMDAC_FP_TG_CONTROL);
+  SHOW_RAMDAC_REG(NV_PRAMDAC_FP_DEBUG_0);
+  SHOW_RAMDAC_REG(NV_PRAMDAC_FP_DEBUG_1);
+
+  SHOW_RAMDAC_REG(NV_PRAMDAC_FP_TMDS_CONTROL);
+  SHOW_RAMDAC_REG(NV_PRAMDAC_FP_TMDS_DATA);
+  SHOW_RAMDAC_REG(0x6808b8);
+  SHOW_RAMDAC_REG(0x6808bc);
   
   dump_vga_regs(0);
   dump_vga_regs(1);
@@ -351,7 +344,6 @@ static struct {
 	const char *name;
 	unsigned address;
 } reg_list[] = {
-  REGLIST(NV40_PFIFO_RAMFC),
 };
 
 void radeon_reg_match(const char *pattern)
@@ -390,26 +382,26 @@ void radeon_reg_set(const char *name, unsigned value)
 
 	if (name[0]=='0' && name[1]=='x') {
 		address = strtoul(&(name[2]), NULL, 16);
-		printf("OLD: %s (%04x)\t0x%08x\n", name, address, radeon_get32(address, name));
+		printf("OLD: %s (%04lx)\t0x%08x\n", name, address, radeon_get32(address, name));
 		radeon_set32(address, name, value);
-		printf("NEW: %s (%04x)\t0x%08x\n", name, address, radeon_get32(address, name));
+		printf("NEW: %s (%04lx)\t0x%08x\n", name, address, radeon_get32(address, name));
 		return;
         }
 	if (name[0] == 'C' && name[2] == ':') {
 		uint8_t crtc = (name[1] == '0') ? 0 : 1;
 		address = strtol(&(name[3]), NULL, 16);
-		printf("OLD: %s (%04x)\t0x%02x\n", name, address, get_vga_crtc_reg(crtc, address));
+		printf("OLD: %s (%04lx)\t0x%02x\n", name, address, get_vga_crtc_reg(crtc, address));
         	set_vga_crtc_reg(crtc, address, value);
-		printf("NEW: %s (%04x)\t0x%02x\n", name, address, get_vga_crtc_reg(crtc, address));
+		printf("NEW: %s (%04lx)\t0x%02x\n", name, address, get_vga_crtc_reg(crtc, address));
 		return;
         }
 	for (i=0;i<sizeof(reg_list)/sizeof(reg_list[0]);i++) {
 		if (fnmatch(name, reg_list[i].name, 0) == 0) {
 			const char *name = reg_list[i].name;
 			address = reg_list[i].address;
-			printf("OLD: %s (%04x)\t0x%08x\n", name, address, radeon_get32(address, name));
+			printf("OLD: %s (%04lx)\t0x%08x\n", name, address, radeon_get32(address, name));
 			radeon_set32(address, name, value);
-			printf("NEW: %s (%04x)\t0x%08x\n", name, address, radeon_get32(address, name));
+			printf("NEW: %s (%04lx)\t0x%08x\n", name, address, radeon_get32(address, name));
 		}
 	}
 }