add support for dumping tmds indirects

2 files changed, 53 insertions, 22 deletions

diff --git a/nouveau_reg.h b/nouveau_reg.h
index 239082f..23e873e 100644
--- a/nouveau_reg.h
+++ b/nouveau_reg.h
@@ -230,14 +230,13 @@
 #define NV40_RAMFC_2088                                          0x4C
 #define NV40_RAMFC_3300                                          0x50
 
+#define NV_PCRTC0_OFFSET            0x00600000
+#define NV_PCRTC1_OFFSET            0x00602000
 #define NV_PRAMDAC0_OFFSET          0x00680000
 #define NV_PRAMDAC1_OFFSET          0x00682000
-#define NV_PCRTC0_OFFSET            0x00600000
 #define NV_PCIO0_OFFSET             0x00601000
 #define NV_PCIO0_SIZE               0x00002000
 
-
-
 #define NV_VGA_CRTCX_REPAINT0		0x19
 #define NV_VGA_CRTCX_REPAINT1		0x1a
 #define NV_VGA_CRTCX_FIFO0		0x1b
@@ -322,3 +321,5 @@
 
 #define NV_RAMDAC_FP_TMDS_DATA      0x8b0
 #define NV_RAMDAC_FP_TMDS_LVDS      0x8b4
+#define NV_RAMDAC_FP_TMDS_OTHER     0x8b8
+#define NV_RAMDAC_FP_TMDS_OTHER2    0x8bc
diff --git a/radeontool.c b/radeontool.c
index c35f619..bf257b6 100644
--- a/radeontool.c
+++ b/radeontool.c
@@ -50,11 +50,14 @@ static unsigned int radeon_get32(unsigned long offset, const char *name)
 	exit(-2);
     };
 #ifdef __powerpc__
+    value = *(unsigned int * volatile)(radeon_cntl_mem+offset);  
+#if 0
     __asm__ __volatile__ ("lwbrx %0,%1,%2\n\t"
 			  "eieio"
 			  : "=r" (value)
 			  : "b" (radeon_cntl_mem), "r"(offset),
 			  "m" (*((volatile unsigned int *)radeon_cntl_mem+offset)));
+#endif
 #else
     value = *(unsigned int * volatile)(radeon_cntl_mem+offset);  
 #endif
@@ -182,6 +185,21 @@ uint8_t get_vga_crtc_reg(int crtc, int reg)
   return retval;
 }
 
+uint32_t get_tmds_index_reg(int index, int reg)
+{
+  uint32_t idx_reg;
+  uint32_t retval;
+
+  if (index == 0)
+	idx_reg = NV_RAMDAC_FP_TMDS_DATA;
+  else
+	idx_reg = NV_RAMDAC_FP_TMDS_OTHER;
+
+  radeon_set32(NV_PRAMDAC0_OFFSET + idx_reg, "FPTMDS", 0x10000 | reg);
+  retval = radeon_get32(NV_PRAMDAC0_OFFSET + idx_reg + 4, "FPTMDS");
+  return retval;
+}
+
 void set_crtc_owner(int crtc)
 {
   int offset;
@@ -195,6 +213,8 @@ void set_crtc_owner(int crtc)
 
 }
 
+
+
 int dump_vga_regs(int crtc)
 {
   int i;
@@ -231,6 +251,15 @@ int dump_vga_regs(int crtc)
   SHOW_VGA_CRTC_REG(NV_VGA_CRTCX_UNK35);
   SHOW_VGA_CRTC_REG(NV_VGA_CRTCX_UNK58);
 }
+
+void dump_tmds_regs(int index)
+{
+  int i;
+
+  for ( i = 0; i < 0x43; i++)
+	printf("TMDS%d: %d:\t%08X\n", index, i, get_tmds_index_reg(index, i));
+
+}
 void radeon_cmd_regs(void)
 {
 	#define SHOW_REG(r) printf("%s\t%08x\n", #r, radeon_get32(r, #r))
@@ -240,27 +269,21 @@ void radeon_cmd_regs(void)
   SHOW_REG(NV_PFIFO_RAMFC);
   SHOW_REG(NV40_PFIFO_RAMFC);
   
-#define SHOW_CRTC0_REG(r) printf("%s0\t%08x\n", #r, radeon_get32(NV_PCRTC0_OFFSET+r, #r))
-#define SHOW_CRTC1_REG(r) printf("%s1\t%08x\n", #r, radeon_get32(NV_PCRTC0_OFFSET+0x2000+r, #r))
-
-  SHOW_CRTC0_REG(NV_CRTC_START);
-  SHOW_CRTC0_REG(NV_CRTC_CURSOR_CONFIG);
-  SHOW_CRTC0_REG(NV_CRTC_HEAD_CONFIG);
-  SHOW_CRTC0_REG(NV_CRTC_081C);
-  SHOW_CRTC0_REG(NV_CRTC_0830);
-  SHOW_CRTC0_REG(NV_CRTC_0834);
-  
-  SHOW_CRTC1_REG(NV_CRTC_START);
-  SHOW_CRTC1_REG(NV_CRTC_CURSOR_CONFIG);
-  SHOW_CRTC1_REG(NV_CRTC_HEAD_CONFIG);
-  SHOW_CRTC1_REG(NV_CRTC_081C);
-  SHOW_CRTC1_REG(NV_CRTC_0830);
-  SHOW_CRTC1_REG(NV_CRTC_0834);
+#define SHOW_CRTC_REG(r) do { printf("%08X: %s0\t%08x\n", NV_PCRTC0_OFFSET+r, #r, radeon_get32(NV_PCRTC0_OFFSET+r, #r)); \
+			      printf("%08X: %s1\t%08x\n", NV_PCRTC1_OFFSET+r, #r, radeon_get32(NV_PCRTC1_OFFSET+r, #r)); \
+			} while(0)
 
-#define SHOW_RAMDAC0_REG(r) do { printf("%s0\t%08x\n", #r, radeon_get32(NV_PRAMDAC0_OFFSET+r, #r)); } while(0)
+  SHOW_CRTC_REG(NV_CRTC_START);
+  SHOW_CRTC_REG(NV_CRTC_CURSOR_CONFIG);
+  SHOW_CRTC_REG(NV_CRTC_HEAD_CONFIG);
+  SHOW_CRTC_REG(NV_CRTC_081C);
+  SHOW_CRTC_REG(NV_CRTC_0830);
+  SHOW_CRTC_REG(NV_CRTC_0834);
 
-#define SHOW_RAMDAC_REG(r) do { printf("%s0\t%08x\n", #r, radeon_get32(NV_PRAMDAC0_OFFSET+r, #r)); \
-	printf("%s1\t%08x\n", #r, radeon_get32(NV_PRAMDAC1_OFFSET+r, #r)); \
+#define SHOW_RAMDAC0_REG(r) do { printf("%08X: %s0\t%08x\n", NV_PRAMDAC0_OFFSET+r, #r, radeon_get32(NV_PRAMDAC0_OFFSET+r, #r)); } while(0)
+
+#define SHOW_RAMDAC_REG(r) do { printf("%08X: %s0\t%08x\n", NV_PRAMDAC0_OFFSET+r, #r, radeon_get32(NV_PRAMDAC0_OFFSET+r, #r)); \
+				printf("%08X: %s1\t%08x\n", NV_PRAMDAC1_OFFSET+r, #r, radeon_get32(NV_PRAMDAC1_OFFSET+r, #r)); \
 } while(0)
 
   SHOW_RAMDAC_REG(NV_RAMDAC_CURSOR_POS);
@@ -288,6 +311,10 @@ void radeon_cmd_regs(void)
   SHOW_RAMDAC_REG(NV_RAMDAC_FP_CONTROL);
   SHOW_RAMDAC_REG(NV_RAMDAC_FP_DEBUG_0);
   SHOW_RAMDAC_REG(NV_RAMDAC_GENERAL_CONTROL);
+  SHOW_RAMDAC_REG(NV_RAMDAC_FP_TMDS_DATA);
+  SHOW_RAMDAC_REG(NV_RAMDAC_FP_TMDS_LVDS);
+  SHOW_RAMDAC_REG(NV_RAMDAC_FP_TMDS_OTHER);
+  SHOW_RAMDAC_REG(NV_RAMDAC_FP_TMDS_OTHER2);
   SHOW_RAMDAC0_REG(NV_RAMDAC_NVPLL);
   SHOW_RAMDAC0_REG(NV_RAMDAC_MPLL);
   SHOW_RAMDAC0_REG(NV_RAMDAC_VPLL);
@@ -303,6 +330,9 @@ void radeon_cmd_regs(void)
   dump_vga_regs(0);
   dump_vga_regs(1);
 
+  dump_tmds_regs(0);
+  dump_tmds_regs(1);
+
 }
 
 #define REGLIST(r) { #r,  r }