Handle cr44 better when dumping regs, add method to set it manually

1 files changed, 30 insertions, 5 deletions

diff --git a/radeontool.c b/radeontool.c
index 11dd366..d6151d2 100644
--- a/radeontool.c
+++ b/radeontool.c
@@ -28,6 +28,7 @@
 
 int debug=0;
 int skip;
+int arch;
 
 /* *radeon_cntl_mem is mapped to the actual device's memory mapped control area. */
 /* Not the address but what it points to is volatile. */
@@ -123,9 +124,12 @@ static void usage(void)
     printf("usage: radeontool [options] [command]\n");
     printf("         --debug            - show a little debug info\n");
     printf("         --skip=1           - use the second radeon card\n");
+    printf("\n");
     printf("         regs               - show a listing of some random registers\n");
     printf("         regmatch <pattern> - show registers matching wildcard pattern\n");
     printf("         regset <pattern> <value> - set registers matching wildcard pattern\n");
+    printf("\n");
+    printf("         owner <value>      - set cr44 to some value (0 (head a), 3 (head b), or 4 (both) suggested)\n");
     exit(-1);
 }
 
@@ -209,18 +213,23 @@ uint32_t get_tmds_index_reg(int index, int reg)
   return retval;
 }
 
-void set_crtc_owner(int crtc)
+void set_crtc_owner(int owner)
 {
   radeon_set8(NV_PRMCIO_CRX__COLOR, "CRTC", NV_CIO_CRE_44);
-  radeon_set8(NV_PRMCIO_CR__COLOR, "CRTC", crtc ? 0x3 : 0x0);
+  radeon_set8(NV_PRMCIO_CR__COLOR, "CRTC", owner);
+
+  if (arch == 0x11) {
+    radeon_set8(NV_PRMCIO_CRX__COLOR, "CRTC", NV_CIO_CRE_2E);
+    radeon_set8(NV_PRMCIO_CR__COLOR, "CRTC", owner);
+    radeon_set8(NV_PRMCIO_CRX__COLOR, "CRTC", NV_CIO_CRE_2E);
+    radeon_set8(NV_PRMCIO_CR__COLOR, "CRTC", owner);
+  }
 }
 
 void dump_vga_regs(int crtc)
 {
   int i;
 
-  set_crtc_owner(crtc);
-
   for (i = 0; i<0x9f; i+=4)
     printf("CRTC%2d %02X\t%02X %02X %02X %02X\n", crtc, i, get_vga_crtc_reg(crtc, i),
 	   get_vga_crtc_reg(crtc, i+1), get_vga_crtc_reg(crtc, i+2), get_vga_crtc_reg(crtc, i+3));
@@ -260,6 +269,13 @@ void dump_tmds_regs(int index)
 }
 void radeon_cmd_regs(void)
 {
+  int init_head = -1;
+
+  if (arch >= 0x17 && arch != 0x1a && arch != 0x20)
+    init_head = get_vga_crtc_reg(0, NV_CIO_CRE_44);
+  else if (arch == 0x11)	// just assume crtc 0
+    init_head = 0;
+
 	#define SHOW_REG(r) printf("%s\t%08x\n", #r, radeon_get32(r, #r))
 
 SHOW_REG(NV_PMC_BOOT_0);
@@ -331,12 +347,16 @@ SHOW_REG(NV_PEXTDEV_BOOT_0);
   SHOW_RAMDAC_REG(0x6808b8);
   SHOW_RAMDAC_REG(0x6808bc);
   
+  set_crtc_owner(0);
+
   dump_vga_regs(0);
   dump_vga_regs(1);
 
+  if (init_head >= 0)
+    set_crtc_owner(init_head);
+
   dump_tmds_regs(0);
   dump_tmds_regs(1);
-
 }
 
 #define REGLIST(r) { #r,  r }
@@ -550,6 +570,7 @@ int main(int argc,char *argv[])
         argv++; argc--;
     };
     map_radeon_cntl_mem();
+    arch = (radeon_get32(NV_PMC_BOOT_0, "NV_PMC_BOOT_0") >> 20) & 0xff;
     if(argc == 2) {
         if(strcmp(argv[1],"regs") == 0) {
             radeon_cmd_regs();
@@ -560,6 +581,10 @@ int main(int argc,char *argv[])
             radeon_reg_match(argv[2]);
             return 0;
 	};
+        if(strcmp(argv[1],"owner") == 0) {
+            set_crtc_owner(strtoul(argv[2], NULL, 0));
+            return 0;
+	};
     } else if(argc == 4) {
 	    if(strcmp(argv[1],"regset") == 0) {
 		    radeon_reg_set(argv[2], strtoul(argv[3], NULL, 0));