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authorDaniel Vetter <daniel.vetter@ffwll.ch>2011-02-22 18:53:56 +0100
committerDaniel Vetter <daniel.vetter@ffwll.ch>2011-02-22 18:53:56 +0100
commit9a71ed93f48f4b319148913a6b56751f6341f078 (patch)
tree4acbca711f51683b434cf1949e6c3b02de48a87d
parenta697fb6acad7992c3d23bb6a663663694782eb7b (diff)
intel: fix relaxed tiling on gen2gen2-b0rked-relaxed-fencing
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
-rw-r--r--intel/intel_bufmgr_gem.c16
1 files changed, 10 insertions, 6 deletions
diff --git a/intel/intel_bufmgr_gem.c b/intel/intel_bufmgr_gem.c
index 3cdffce1..9b324d95 100644
--- a/intel/intel_bufmgr_gem.c
+++ b/intel/intel_bufmgr_gem.c
@@ -744,7 +744,7 @@ drm_intel_gem_bo_alloc_tiled(drm_intel_bufmgr *bufmgr, const char *name,
uint32_t tiling;
do {
- unsigned long aligned_y;
+ unsigned long aligned_y, height_alignment;
tiling = *tiling_mode;
@@ -760,12 +760,16 @@ drm_intel_gem_bo_alloc_tiled(drm_intel_bufmgr *bufmgr, const char *name,
* too so we try to be careful.
*/
aligned_y = y;
- if (tiling == I915_TILING_NONE)
- aligned_y = ALIGN(y, 2);
- else if (tiling == I915_TILING_X)
- aligned_y = ALIGN(y, 8);
+ height_alignment = 2;
+
+ if (tiling == I915_TILING_X)
+ height_alignment = 8;
else if (tiling == I915_TILING_Y)
- aligned_y = ALIGN(y, 32);
+ height_alignment = 32;
+ /* i8xx has a interleaved 2-row tile layout */
+ if (IS_GEN2(bufmgr_gem))
+ height_alignment *= 2;
+ aligned_y = ALIGN(y, height_alignment);
stride = x * cpp;
stride = drm_intel_gem_bo_tile_pitch(bufmgr_gem, stride, tiling_mode);