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| author | Eugeni Dodonov <eugeni.dodonov@intel.com> | 2012-06-21 14:31:34 -0300 |
|---|---|---|
| committer | Eugeni Dodonov <eugeni.dodonov@intel.com> | 2012-06-21 14:31:34 -0300 |
| commit | c6fe31bc473a7ae44bc42bad7da5faca3c924821 (patch) | |
| tree | c7f317fc372f5c7a3a0256ace535538abbe28ed6 | |
| parent | f7e356d9cd7795de055a9f3c13bb33f5c9bea01f (diff) | |
intel_reg_dumper: use intel_register_access_init/fini
We need to hold forcewake lock in order to be able to read GT registers.
Otherwise, when the GPU is in RC6 mode, we'll read all zeros.
Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
| -rw-r--r-- | tools/intel_reg_dumper.c | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/tools/intel_reg_dumper.c b/tools/intel_reg_dumper.c index 913d13be..767363d9 100644 --- a/tools/intel_reg_dumper.c +++ b/tools/intel_reg_dumper.c @@ -2177,7 +2177,7 @@ int main(int argc, char** argv) pci_dev = intel_get_pci_device(); devid = pci_dev->device_id; - intel_get_mmio(pci_dev); + intel_register_access_init(pci_dev, 1); if (HAS_PCH_SPLIT(devid)) intel_check_pch(); @@ -2201,5 +2201,7 @@ int main(int argc, char** argv) if (IS_HASWELL(devid)) intel_dump_regs(haswell_debug_regs); + + intel_register_access_fini(); return 0; } |