drm/i915: fix ibx/cpt/ppt dpll limitspll-limits-mess

Now this was broken in pretty fundamental ways:
- M1/M2 have been consistently off by 2 and used doc values instead of
  the two less registers values our code expects.
- M/N limits often were too small by seemingly arbitrary amounts. I
  suspect this started to work around issues due to the wrong M1/M2
  limits.

Rectify this all and consolidate the limits a bit with a #define where
the docs say that they should be equal.

Still waiting for confirmation from Art Ranyan, our display hw
designer.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

1 files changed, 11 insertions, 25 deletions

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index aa25476aaadf..efb555b098f3 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -294,18 +294,16 @@ static const intel_limit_t intel_limits_pineview_lvds = {
 	.find_pll = intel_find_best_PLL,
 };
 
-/* Ironlake / Sandybridge
- *
- * We calculate clock using (register_value + 2) for N/M1/M2, so here
- * the range value for them is (actual_value - 2).
- */
+#define ILK_DPLL_M_N_LIMITS \
+	.n = { .min = 1, .max = 6 }, \
+	.m = { .min = 79, .max = 127 }, \
+	.m1 = { .min = 10, .max = 20 }, \
+	.m2 = { .min = 3, .max = 7 }, \
+
 static const intel_limit_t intel_limits_ironlake_dac = {
 	.dot = { .min = 25000, .max = 350000 },
 	.vco = { .min = 1760000, .max = 3510000 },
-	.n = { .min = 1, .max = 5 },
-	.m = { .min = 79, .max = 127 },
-	.m1 = { .min = 12, .max = 22 },
-	.m2 = { .min = 5, .max = 9 },
+	ILK_DPLL_M_N_LIMITS
 	.p = { .min = 5, .max = 80 },
 	.p1 = { .min = 1, .max = 8 },
 	.p2 = { .dot_limit = 225000,
@@ -316,10 +314,7 @@ static const intel_limit_t intel_limits_ironlake_dac = {
 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 	.dot = { .min = 25000, .max = 350000 },
 	.vco = { .min = 1760000, .max = 3510000 },
-	.n = { .min = 1, .max = 3 },
-	.m = { .min = 79, .max = 118 },
-	.m1 = { .min = 12, .max = 22 },
-	.m2 = { .min = 5, .max = 9 },
+	ILK_DPLL_M_N_LIMITS
 	.p = { .min = 28, .max = 112 },
 	.p1 = { .min = 2, .max = 8 },
 	.p2 = { .dot_limit = 225000,
@@ -330,10 +325,7 @@ static const intel_limit_t intel_limits_ironlake_single_lvds = {
 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 	.dot = { .min = 25000, .max = 350000 },
 	.vco = { .min = 1760000, .max = 3510000 },
-	.n = { .min = 1, .max = 3 },
-	.m = { .min = 79, .max = 127 },
-	.m1 = { .min = 12, .max = 22 },
-	.m2 = { .min = 5, .max = 9 },
+	ILK_DPLL_M_N_LIMITS
 	.p = { .min = 14, .max = 56 },
 	.p1 = { .min = 2, .max = 8 },
 	.p2 = { .dot_limit = 225000,
@@ -345,10 +337,7 @@ static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 	.dot = { .min = 25000, .max = 350000 },
 	.vco = { .min = 1760000, .max = 3510000 },
-	.n = { .min = 1, .max = 2 },
-	.m = { .min = 79, .max = 126 },
-	.m1 = { .min = 12, .max = 22 },
-	.m2 = { .min = 5, .max = 9 },
+	ILK_DPLL_M_N_LIMITS
 	.p = { .min = 28, .max = 112 },
 	.p1 = { .min = 2, .max = 8 },
 	.p2 = { .dot_limit = 225000,
@@ -359,10 +348,7 @@ static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 	.dot = { .min = 25000, .max = 350000 },
 	.vco = { .min = 1760000, .max = 3510000 },
-	.n = { .min = 1, .max = 3 },
-	.m = { .min = 79, .max = 126 },
-	.m1 = { .min = 12, .max = 22 },
-	.m2 = { .min = 5, .max = 9 },
+	ILK_DPLL_M_N_LIMITS
 	.p = { .min = 14, .max = 42 },
 	.p1 = { .min = 2, .max = 6 },
 	.p2 = { .dot_limit = 225000,