summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorChia-I Wu <olv@lunarg.com>2014-01-28 13:29:34 +0800
committerDaniel Vetter <daniel.vetter@ffwll.ch>2014-01-30 13:09:30 +0100
commit116f2b6da868dec7539103574d0421cd6221e931 (patch)
tree07ec5acec97aacb63cf68ae40105fff8f0010549
parentfe27c606625299ec6237ad420e9c2f961fa3bf3d (diff)
drm/i915: enable HiZ Raw Stall Optimization on IVB
The optimization helps IVB too. No piglit regression. Signed-off-by: Chia-I Wu <olv@lunarg.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
-rw-r--r--drivers/gpu/drm/i915/intel_pm.c4
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 1a1eec64ecf..3c79b634288 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4866,6 +4866,10 @@ static void ivybridge_init_clock_gating(struct drm_device *dev)
gen7_setup_fixed_func_scheduler(dev_priv);
+ /* enable HiZ Raw Stall Optimization */
+ I915_WRITE(CACHE_MODE_0_GEN7,
+ _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
+
/* WaDisable4x2SubspanOptimization:ivb */
I915_WRITE(CACHE_MODE_1,
_MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));