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authorAndre Nogueira <andre.neo.net@gmail.com>2011-02-09 21:27:33 +0000
committerDave Jones <davej@redhat.com>2011-02-09 17:01:05 -0500
commitbaac19e85f3265c68d264724b79f5bcd3c95e91d (patch)
treeaab632044c728aa29634fcbfc285962f5e44f3e7 /apic.h
parentca28d4ef5a2cb40e64674aebcdf5427d8cf33511 (diff)
Dump APIC registers
I have developed a patch that dumps the APIC registers. This patch was developed based on information available in "Intel 64 and IA-32 Architectures Software Developer's Manual Volume 3A: System Programming Guide", chapter 10 - ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC).
Diffstat (limited to 'apic.h')
-rw-r--r--apic.h44
1 files changed, 44 insertions, 0 deletions
diff --git a/apic.h b/apic.h
new file mode 100644
index 0000000..e412715
--- /dev/null
+++ b/apic.h
@@ -0,0 +1,44 @@
+#ifndef _APIC_H
+#define _APIC_H
+
+#define IA32_APIC_BASE_MSR 0x1B
+
+#define APIC_REGISTER_SPACE 4096
+#define APIC_REGISTER_ALIGNED_SIZE 4
+
+#define PAGE_OFFSET(addr) ((unsigned long)(addr) & (getpagesize() - 1))
+
+enum apic_register_offset
+{
+ APIC_ID = 0x2,
+ APIC_VER = 0x3,
+ APIC_TPR = 0x8,
+ APIC_APR = 0x9,
+ APIC_PPR = 0xA,
+ APIC_EOI = 0xB,
+ APIC_RRD = 0xC,
+ APIC_LDR = 0xD,
+ APIC_DFR = 0xE,
+ APIC_SIVR = 0xF,
+ APIC_ISR = 0x10,
+ APIC_TMR = 0x18,
+ APIC_IRR = 0x20,
+ APIC_ESR = 0x28,
+ APIC_LVT = 0x2F,
+ APIC_ICR0 = 0x30,
+ APIC_ICR1 = 0x31,
+ APIC_LVTT = 0x32,
+ APIC_LVTTS = 0x33,
+ APIC_LVTPC = 0x34,
+ APIC_LVT0 = 0x35,
+ APIC_LVT1 = 0x36,
+ APIC_LVTER = 0x37,
+ APIC_TICR = 0x38,
+ APIC_TCCR = 0x39,
+ APIC_TDCR = 0x3E,
+};
+
+#include <fcntl.h>
+#include <sys/mman.h>
+
+#endif /* _APIC_H */