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| author | Andreas Herrmann <andreas.herrmann3@amd.com> | 2011-04-05 20:25:44 +0200 |
|---|---|---|
| committer | Dave Jones <davej@redhat.com> | 2011-04-05 18:51:04 -0400 |
| commit | b3517fee4e88243c7a22f0d7ba8d75179d2c2c42 (patch) | |
| tree | 03f51567a846269d9749e554f68e3f70ccb6aafa | |
| parent | b34a661cf5925866dbc9163b3c824f783f9da27b (diff) | |
x86info, AMD: Fix L3 cache reporting if no L3 is available
Signed-off-by: Andreas Herrmann <andreas.herrmann3@amd.com>
| -rw-r--r-- | AMD/identify.c | 18 |
1 files changed, 11 insertions, 7 deletions
diff --git a/AMD/identify.c b/AMD/identify.c index 5d9f897..8d6f491 100644 --- a/AMD/identify.c +++ b/AMD/identify.c @@ -295,14 +295,18 @@ void decode_AMD_cacheinfo(struct cpudata *cpu) printf("lines per tag=%u\t", (ecx >> 8) & 0x0f); printf("line size=%u bytes.\n", ecx & 0xff); if (family(cpu) == 0x10) { - /* family 0x10 has shared L3 cache */ printf("L3 (shared) cache:\n\t"); - printf("Size: %uKb\t", - (edx >> 18) * 512); - do_l2assoc((edx >> 12) & 0x0f); - printf("\n\t"); - printf("lines per tag=%u\t", (edx >> 8) & 0x0f); - printf("line size=%u bytes.\n", edx & 0xff); + if (!(edx >> 18)) + printf("none/disabled\n"); + else { + /* family 0x10 has shared L3 cache */ + printf("Size: %uKb\t", + (edx >> 18) * 512); + do_l2assoc((edx >> 12) & 0x0f); + printf("\n\t"); + printf("lines per tag=%u\t", (edx >> 8) & 0x0f); + printf("line size=%u bytes.\n", edx & 0xff); + } } } |