Some notes about size directives

1 files changed, 33 insertions, 0 deletions

diff --git a/TODO b/TODO
index 2c971b0..c31634c 100644
--- a/TODO
+++ b/TODO
@@ -1,3 +1,36 @@
+- Size directives
+
+  - There are a number of cases where the op size can't be inferred
+    from the instruction. For example,
+
+    	 movzx eax, PTR(ebx)
+
+    How many bytes should be zero-extended? In this case we have coped
+    by simply adding movzx.8/16/32 variants.
+
+    But there are other cases, like 
+
+    	      add  PTR(ebx), imm8
+
+    which can have four sizes two. That goes for all the ALU ops in
+    fact.
+
+    Proposed solution: Add new OP_MEM8/16/32/64 and RIP_REL8/16/32/64
+    types that are designed such that they can be generated with
+
+    	     BYTE_PTR
+	     WORD_PTR
+	     DWORD_PTR
+	     QWORD_PTR
+
+    macros that are appended to the INDEX/BASE/PTR/RIPREL macros.
+
+    - The A_MEM will include the new OP_MEM<size> so that you can give
+      the size directive if you want to. And compute_op_size() will
+      check that if you do, it is correct.
+
+    - Some instructions will only allow the size directed variants.
+    
 - The pextrw instruction got a new variant in SSE 4.1 where the
 destination can now be either a memory location or a register. In
 earlier versions it could only be a register. That means this code