diff options
author | Søren Sandmann Pedersen <ssp@redhat.com> | 2013-09-08 17:38:50 -0400 |
---|---|---|
committer | Søren Sandmann Pedersen <ssp@redhat.com> | 2013-09-08 17:38:50 -0400 |
commit | 9f883beac06e8763ae7352a38b6175a11c0ab836 (patch) | |
tree | b4a2910d26fa947073002e7abd1901b75de9e14f | |
parent | db943fba243f0db60c967fbbd720650a705f5b35 (diff) |
Add read/write information to all instructions
The instruction identifier is extended with another field that encodes
which of the operands are read and written. This information is
expected to be useful for liveness analysis.
TODO: Consider if there is some way to verify programmatically that
all instructions behave as the read/write information describes. For
example, generate a program that runs one instruction on registers and
verify that "read" registers don't change
On a similar note -- verify that all instructions that are supposed to
be able to run on the current machine will actually run (and not #UD).
-rw-r--r-- | simplex86.c | 4 | ||||
-rw-r--r-- | simplex86.h | 606 |
2 files changed, 316 insertions, 294 deletions
diff --git a/simplex86.c b/simplex86.c index 3e24df6..812e04a 100644 --- a/simplex86.c +++ b/simplex86.c @@ -841,14 +841,14 @@ static const char inames[][12] = { "invalid", -#define PROCESS_INSTRUCTION(name, n_ops) \ +#define PROCESS_INSTRUCTION(name, rwinfo, n_ops) \ #name, ALL_INSTRUCTIONS }; #define GET_NAME(inst) \ - inames[(inst) >> 9] + inames[GET_SERIAL(inst)] static void sanity_check (void) diff --git a/simplex86.h b/simplex86.h index f4751f5..98b2ff6 100644 --- a/simplex86.h +++ b/simplex86.h @@ -259,307 +259,323 @@ typedef enum #define DEFINE_LABEL(name) \ I_label, LABEL (name) -#define PROCESS_SIMD(name, n_ops, n_vops) \ - PROCESS_INSTRUCTION (name, n_ops) \ - PROCESS_INSTRUCTION (v##name, n_vops) +#define PROCESS_SIMD(name, rwinfo, n_ops, rwinfo_v, n_vops) \ + PROCESS_INSTRUCTION (name, rwinfo, n_ops) \ + PROCESS_INSTRUCTION (v##name, rwinfo_v, n_vops) -#define PROCESS_SIMD_FLOAT_SINGLE(name, n_ops, n_vops) \ - PROCESS_SIMD (name##ps, n_ops, n_vops) \ - PROCESS_SIMD (name##ss, n_ops, n_vops) +#define PROCESS_SIMD_FLOAT_SINGLE(name, rw, n_ops, vrw, n_vops) \ + PROCESS_SIMD (name##ps, rw, n_ops, vrw, n_vops) \ + PROCESS_SIMD (name##ss, rw, n_ops, vrw, n_vops) -#define PROCESS_SIMD_FLOAT_DOUBLE(name, n_ops, n_vops) \ - PROCESS_SIMD (name##pd, n_ops, n_vops) \ - PROCESS_SIMD (name##sd, n_ops, n_vops) +#define PROCESS_SIMD_FLOAT_DOUBLE(name, rw, n_ops, vrw, n_vops) \ + PROCESS_SIMD (name##pd, rw, n_ops, vrw, n_vops) \ + PROCESS_SIMD (name##sd, rw, n_ops, vrw, n_vops) -#define PROCESS_SIMD_FLOAT(name, n_ops, n_vops) \ - PROCESS_SIMD_FLOAT_SINGLE(name, n_ops, n_vops) \ - PROCESS_SIMD_FLOAT_DOUBLE(name, n_ops, n_vops) +#define PROCESS_SIMD_FLOAT(name, rw, n_ops, vrw, n_vops) \ + PROCESS_SIMD_FLOAT_SINGLE(name, rw, n_ops, vrw, n_vops) \ + PROCESS_SIMD_FLOAT_DOUBLE(name, rw, n_ops, vrw, n_vops) #define PROCESS_XOP_COMPARE(type) \ - PROCESS_INSTRUCTION (vpcomlt##type, 3) \ - PROCESS_INSTRUCTION (vpcomle##type, 3) \ - PROCESS_INSTRUCTION (vpcomgt##type, 3) \ - PROCESS_INSTRUCTION (vpcomge##type, 3) \ - PROCESS_INSTRUCTION (vpcome##type, 3) \ - PROCESS_INSTRUCTION (vpcomne##type, 3) \ - PROCESS_INSTRUCTION (vpcomfalse##type, 3) \ - PROCESS_INSTRUCTION (vpcomtrue##type, 3) + PROCESS_INSTRUCTION (vpcomlt##type, WRR, 3) \ + PROCESS_INSTRUCTION (vpcomle##type, WRR, 3) \ + PROCESS_INSTRUCTION (vpcomgt##type, WRR, 3) \ + PROCESS_INSTRUCTION (vpcomge##type, WRR, 3) \ + PROCESS_INSTRUCTION (vpcome##type, WRR, 3) \ + PROCESS_INSTRUCTION (vpcomne##type, WRR, 3) \ + PROCESS_INSTRUCTION (vpcomfalse##type, WRR, 3) \ + PROCESS_INSTRUCTION (vpcomtrue##type, WRR, 3) + +#define R (0x01) /* Read */ +#define W (0x02) /* Write */ +#define B (0x03) /* Both (Read-Write) */ +#define NA (0x00) /* Not applicable (No variables) */ + +#define RR ((R << 2) | R) +#define WR ((R << 2) | W) +#define BR ((R << 2) | B) +#define BB ((B << 2) | B) + +#define BRR ((R << 4) | (R << 2) | B) +#define WRR ((R << 4) | (R << 2) | W) +#define BRB ((B << 4) | (R << 2) | B) +#define WRRR ((R << 6) | (R << 4) | (R << 2) | W) +#define BRRR ((R << 6) | (R << 4) | (R << 2) | B) #define ALL_INSTRUCTIONS \ - PROCESS_INSTRUCTION (dq, 2) \ - PROCESS_INSTRUCTION (dd, 1) \ - PROCESS_INSTRUCTION (dw, 1) \ - PROCESS_INSTRUCTION (db, 1) \ - PROCESS_INSTRUCTION (cbw, 0) \ - PROCESS_INSTRUCTION (cwde, 0) \ - PROCESS_INSTRUCTION (cdqe, 0) \ - PROCESS_INSTRUCTION (bswap, 1) \ - PROCESS_INSTRUCTION (movbe, 2) \ - PROCESS_INSTRUCTION (label, 1) \ - PROCESS_INSTRUCTION (align, 1) \ - PROCESS_INSTRUCTION (lock, 0) \ - PROCESS_INSTRUCTION (pushf, 0) \ - PROCESS_INSTRUCTION (popf, 0) \ - PROCESS_INSTRUCTION (cpuid, 0) \ - PROCESS_INSTRUCTION (xgetbv, 0) \ - PROCESS_INSTRUCTION (nop, 0) \ - PROCESS_INSTRUCTION (nop1, 1) \ - PROCESS_INSTRUCTION (ret, 0) \ - PROCESS_INSTRUCTION (push, 1) \ - PROCESS_INSTRUCTION (pop, 1) \ - PROCESS_INSTRUCTION (lea, 2) \ - PROCESS_INSTRUCTION (xchg, 2) \ - PROCESS_INSTRUCTION (bsf, 2) \ - PROCESS_INSTRUCTION (bsr, 2) \ - PROCESS_INSTRUCTION (mfence, 0) \ - PROCESS_INSTRUCTION (lfence, 0) \ - PROCESS_INSTRUCTION (mov, 2) \ - PROCESS_INSTRUCTION (movabs, 3) \ - PROCESS_INSTRUCTION (movd, 2) \ - PROCESS_INSTRUCTION (vmovd, 2) \ - PROCESS_INSTRUCTION (movq, 2) \ - PROCESS_INSTRUCTION (vmovq, 2) \ - PROCESS_INSTRUCTION (movq2dq, 2) \ - PROCESS_INSTRUCTION (shrd, 3) \ - PROCESS_INSTRUCTION (shld, 3) \ - PROCESS_INSTRUCTION (rdtsc, 0) \ - PROCESS_INSTRUCTION (rdtscp, 0) \ - PROCESS_INSTRUCTION (clflush, 1) \ - PROCESS_INSTRUCTION (test, 2) \ - PROCESS_INSTRUCTION (clc, 0) \ - PROCESS_INSTRUCTION (cld, 0) \ - PROCESS_INSTRUCTION (add, 2) \ - PROCESS_INSTRUCTION (or, 2) \ - PROCESS_INSTRUCTION (adc, 2) \ - PROCESS_INSTRUCTION (sbb, 2) \ - PROCESS_INSTRUCTION (and, 2) \ - PROCESS_INSTRUCTION (sub, 2) \ - PROCESS_INSTRUCTION (xor, 2) \ - PROCESS_INSTRUCTION (cmp, 2) \ - PROCESS_INSTRUCTION (rol, 2) \ - PROCESS_INSTRUCTION (ror, 2) \ - PROCESS_INSTRUCTION (rcl, 2) \ - PROCESS_INSTRUCTION (rcr, 2) \ - PROCESS_INSTRUCTION (shl, 2) \ - PROCESS_INSTRUCTION (shr, 2) \ - PROCESS_INSTRUCTION (sal, 2) \ - PROCESS_INSTRUCTION (sar, 2) \ - PROCESS_INSTRUCTION (movzx, 2) \ - PROCESS_INSTRUCTION (movsx, 2) \ - PROCESS_INSTRUCTION (jmp, 1) \ - PROCESS_INSTRUCTION (call, 1) \ - PROCESS_INSTRUCTION (ja, 1) \ - PROCESS_INSTRUCTION (jae, 1) \ - PROCESS_INSTRUCTION (jb, 1) \ - PROCESS_INSTRUCTION (jbe, 1) \ - PROCESS_INSTRUCTION (jc, 1) \ - PROCESS_INSTRUCTION (je, 1) \ - PROCESS_INSTRUCTION (jg, 1) \ - PROCESS_INSTRUCTION (jge, 1) \ - PROCESS_INSTRUCTION (jl, 1) \ - PROCESS_INSTRUCTION (jle, 1) \ - PROCESS_INSTRUCTION (jna, 1) \ - PROCESS_INSTRUCTION (jnae, 1) \ - PROCESS_INSTRUCTION (jnb, 1) \ - PROCESS_INSTRUCTION (jnbe, 1) \ - PROCESS_INSTRUCTION (jnc, 1) \ - PROCESS_INSTRUCTION (jne, 1) \ - PROCESS_INSTRUCTION (jng, 1) \ - PROCESS_INSTRUCTION (jnge, 1) \ - PROCESS_INSTRUCTION (jnl, 1) \ - PROCESS_INSTRUCTION (jnle, 1) \ - PROCESS_INSTRUCTION (jno, 1) \ - PROCESS_INSTRUCTION (jnp, 1) \ - PROCESS_INSTRUCTION (jns, 1) \ - PROCESS_INSTRUCTION (jnz, 1) \ - PROCESS_INSTRUCTION (jo, 1) \ - PROCESS_INSTRUCTION (jp, 1) \ - PROCESS_INSTRUCTION (jpe, 1) \ - PROCESS_INSTRUCTION (jpo, 1) \ - PROCESS_INSTRUCTION (js, 1) \ - PROCESS_INSTRUCTION (jz, 1) \ - PROCESS_INSTRUCTION (not, 1) \ - PROCESS_INSTRUCTION (neg, 1) \ - PROCESS_INSTRUCTION (mul, 1) \ + PROCESS_INSTRUCTION (dq, RR, 2) \ + PROCESS_INSTRUCTION (dd, R, 1) \ + PROCESS_INSTRUCTION (dw, R, 1) \ + PROCESS_INSTRUCTION (db, R, 1) \ + PROCESS_INSTRUCTION (cbw, NA, 0) \ + PROCESS_INSTRUCTION (cwde, NA, 0) \ + PROCESS_INSTRUCTION (cdqe, NA, 0) \ + PROCESS_INSTRUCTION (bswap, B, 1) \ + PROCESS_INSTRUCTION (movbe, WR, 2) \ + PROCESS_INSTRUCTION (label, R, 1) \ + PROCESS_INSTRUCTION (align, R, 1) \ + PROCESS_INSTRUCTION (lock, NA, 0) \ + PROCESS_INSTRUCTION (pushf, NA, 0) \ + PROCESS_INSTRUCTION (popf, NA, 0) \ + PROCESS_INSTRUCTION (cpuid, NA, 0) \ + PROCESS_INSTRUCTION (xgetbv, NA, 0) \ + PROCESS_INSTRUCTION (nop, NA, 0) \ + PROCESS_INSTRUCTION (nop1, NA, 1) \ + PROCESS_INSTRUCTION (ret, NA, 0) \ + PROCESS_INSTRUCTION (push, R, 1) \ + PROCESS_INSTRUCTION (pop, W, 1) \ + PROCESS_INSTRUCTION (lea, WR, 2) \ + PROCESS_INSTRUCTION (xchg, BB, 2) \ + PROCESS_INSTRUCTION (bsf, WR, 2) \ + PROCESS_INSTRUCTION (bsr, WR, 2) \ + PROCESS_INSTRUCTION (mfence, NA, 0) \ + PROCESS_INSTRUCTION (lfence, NA, 0) \ + PROCESS_INSTRUCTION (mov, WR, 2) \ + PROCESS_INSTRUCTION (movabs, WR, 3) \ + PROCESS_INSTRUCTION (movd, WR, 2) \ + PROCESS_INSTRUCTION (vmovd, WR, 2) \ + PROCESS_INSTRUCTION (movq, WR, 2) \ + PROCESS_INSTRUCTION (vmovq, WR, 2) \ + PROCESS_INSTRUCTION (movq2dq, WR, 2) \ + PROCESS_INSTRUCTION (shrd, BRR, 3) \ + PROCESS_INSTRUCTION (shld, BRR, 3) \ + PROCESS_INSTRUCTION (rdtsc, NA, 0) \ + PROCESS_INSTRUCTION (rdtscp, NA, 0) \ + PROCESS_INSTRUCTION (clflush, R, 1) \ + PROCESS_INSTRUCTION (test, RR, 2) \ + PROCESS_INSTRUCTION (clc, NA, 0) \ + PROCESS_INSTRUCTION (cld, NA, 0) \ + PROCESS_INSTRUCTION (add, BR, 2) \ + PROCESS_INSTRUCTION (or, BR, 2) \ + PROCESS_INSTRUCTION (adc, BR, 2) \ + PROCESS_INSTRUCTION (sbb, BR, 2) \ + PROCESS_INSTRUCTION (and, BR, 2) \ + PROCESS_INSTRUCTION (sub, BR, 2) \ + PROCESS_INSTRUCTION (xor, BR, 2) \ + PROCESS_INSTRUCTION (cmp, RR, 2) \ + PROCESS_INSTRUCTION (rol, BR, 2) \ + PROCESS_INSTRUCTION (ror, BR, 2) \ + PROCESS_INSTRUCTION (rcl, BR, 2) \ + PROCESS_INSTRUCTION (rcr, BR, 2) \ + PROCESS_INSTRUCTION (shl, BR, 2) \ + PROCESS_INSTRUCTION (shr, BR, 2) \ + PROCESS_INSTRUCTION (sal, BR, 2) \ + PROCESS_INSTRUCTION (sar, BR, 2) \ + PROCESS_INSTRUCTION (movzx, WR, 2) \ + PROCESS_INSTRUCTION (movsx, WR, 2) \ + PROCESS_INSTRUCTION (jmp, R, 1) \ + PROCESS_INSTRUCTION (call, R, 1) \ + PROCESS_INSTRUCTION (ja, R, 1) \ + PROCESS_INSTRUCTION (jae, R, 1) \ + PROCESS_INSTRUCTION (jb, R, 1) \ + PROCESS_INSTRUCTION (jbe, R, 1) \ + PROCESS_INSTRUCTION (jc, R, 1) \ + PROCESS_INSTRUCTION (je, R, 1) \ + PROCESS_INSTRUCTION (jg, R, 1) \ + PROCESS_INSTRUCTION (jge, R, 1) \ + PROCESS_INSTRUCTION (jl, R, 1) \ + PROCESS_INSTRUCTION (jle, R, 1) \ + PROCESS_INSTRUCTION (jna, R, 1) \ + PROCESS_INSTRUCTION (jnae, R, 1) \ + PROCESS_INSTRUCTION (jnb, R, 1) \ + PROCESS_INSTRUCTION (jnbe, R, 1) \ + PROCESS_INSTRUCTION (jnc, R, 1) \ + PROCESS_INSTRUCTION (jne, R, 1) \ + PROCESS_INSTRUCTION (jng, R, 1) \ + PROCESS_INSTRUCTION (jnge, R, 1) \ + PROCESS_INSTRUCTION (jnl, R, 1) \ + PROCESS_INSTRUCTION (jnle, R, 1) \ + PROCESS_INSTRUCTION (jno, R, 1) \ + PROCESS_INSTRUCTION (jnp, R, 1) \ + PROCESS_INSTRUCTION (jns, R, 1) \ + PROCESS_INSTRUCTION (jnz, R, 1) \ + PROCESS_INSTRUCTION (jo, R, 1) \ + PROCESS_INSTRUCTION (jp, R, 1) \ + PROCESS_INSTRUCTION (jpe, R, 1) \ + PROCESS_INSTRUCTION (jpo, R, 1) \ + PROCESS_INSTRUCTION (js, R, 1) \ + PROCESS_INSTRUCTION (jz, R, 1) \ + PROCESS_INSTRUCTION (not, B, 1) \ + PROCESS_INSTRUCTION (neg, B, 1) \ + PROCESS_INSTRUCTION (mul, B, 1) \ /* The imul instruction has three different forms, with \ * one, two, and three operands respectively. Since we rely \ * on the ability to determine the number of operands based on \ * the mnemonic alone, we have to make up three different \ * instruction names. \ */ \ - PROCESS_INSTRUCTION (imul1, 1) \ - PROCESS_INSTRUCTION (imul2, 2) \ - PROCESS_INSTRUCTION (imul3, 3) \ - PROCESS_SIMD (movdqa, 2, 2) \ - PROCESS_SIMD (movdqu, 2, 2) \ - PROCESS_SIMD (lddqu, 2, 2) \ - PROCESS_SIMD (palignr, 3, 4) \ - PROCESS_SIMD (packsswb, 2, 3) \ - PROCESS_SIMD (packssdw, 2, 3) \ - PROCESS_SIMD (packuswb, 2, 3) \ - PROCESS_SIMD (pand, 2, 3) \ - PROCESS_SIMD (pandn, 2, 3) \ - PROCESS_SIMD (por, 2, 3) \ - PROCESS_SIMD (pxor, 2, 3) \ - PROCESS_SIMD (pavgb, 2, 3) \ - PROCESS_SIMD (pavgw, 2, 3) \ - PROCESS_SIMD (paddb, 2, 3) \ - PROCESS_SIMD (paddw, 2, 3) \ - PROCESS_SIMD (paddd, 2, 3) \ - PROCESS_SIMD (paddq, 2, 3) \ - PROCESS_SIMD (paddsb, 2, 3) \ - PROCESS_SIMD (paddsw, 2, 3) \ - PROCESS_SIMD (paddusb, 2, 3) \ - PROCESS_SIMD (paddusw, 2, 3) \ - PROCESS_SIMD (pcmpeqb, 2, 3) \ - PROCESS_SIMD (pcmpeqw, 2, 3) \ - PROCESS_SIMD (pcmpeqd, 2, 3) \ - PROCESS_SIMD (pcmpgtb, 2, 3) \ - PROCESS_SIMD (pcmpgtw, 2, 3) \ - PROCESS_SIMD (pcmpgtd, 2, 3) \ - PROCESS_SIMD (pmaddwd, 2, 3) \ - PROCESS_SIMD (pmaxsw, 2, 3) \ - PROCESS_SIMD (pmaxub, 2, 3) \ - PROCESS_SIMD (pminsw, 2, 3) \ - PROCESS_SIMD (pminub, 2, 3) \ - PROCESS_SIMD (pmulhuw, 2, 3) \ - PROCESS_SIMD (pmulhw, 2, 3) \ - PROCESS_SIMD (pmullw, 2, 3) \ - PROCESS_SIMD (pmuludq, 2, 3) \ - PROCESS_SIMD (psadbw, 2, 3) \ - PROCESS_SIMD (psubb, 2, 3) \ - PROCESS_SIMD (psubw, 2, 3) \ - PROCESS_SIMD (psubd, 2, 3) \ - PROCESS_SIMD (psubq, 2, 3) \ - PROCESS_SIMD (psubsb, 2, 3) \ - PROCESS_SIMD (psubsw, 2, 3) \ - PROCESS_SIMD (psubusb, 2, 3) \ - PROCESS_SIMD (psubusw, 2, 3) \ - PROCESS_SIMD (punpckhbw, 2, 3) \ - PROCESS_SIMD (punpckhwd, 2, 3) \ - PROCESS_SIMD (punpckhdq, 2, 3) \ - PROCESS_SIMD (punpcklbw, 2, 3) \ - PROCESS_SIMD (punpcklwd, 2, 3) \ - PROCESS_SIMD (punpckldq, 2, 3) \ - PROCESS_SIMD (psllw, 2, 3) \ - PROCESS_SIMD (pslld, 2, 3) \ - PROCESS_SIMD (psllq, 2, 3) \ - PROCESS_SIMD (psrlw, 2, 3) \ - PROCESS_SIMD (psrld, 2, 3) \ - PROCESS_SIMD (psrlq, 2, 3) \ - PROCESS_SIMD (psraw, 2, 3) \ - PROCESS_SIMD (psrad, 2, 3) \ - PROCESS_SIMD (pinsrw, 3, 4) \ - PROCESS_SIMD (pextrw, 3, 3) \ - PROCESS_SIMD (pabsb, 2, 2) \ - PROCESS_SIMD (pabsw, 2, 2) \ - PROCESS_SIMD (pabsd, 2, 2) \ - PROCESS_SIMD (ptest, 2, 2) \ - PROCESS_SIMD (phminposuw, 2, 2) \ - PROCESS_SIMD (pmovsxbw, 2, 2) \ - PROCESS_SIMD (pmovzxbw, 2, 2) \ - PROCESS_SIMD (pmovsxbd, 2, 2) \ - PROCESS_SIMD (pmovzxbd, 2, 2) \ - PROCESS_SIMD (pmovsxbq, 2, 2) \ - PROCESS_SIMD (pmovzxbq, 2, 2) \ - PROCESS_SIMD (pmovsxwd, 2, 2) \ - PROCESS_SIMD (pmovzxwd, 2, 2) \ - PROCESS_SIMD (pmovsxwq, 2, 2) \ - PROCESS_SIMD (pmovzxwq, 2, 2) \ - PROCESS_SIMD (pmovsxdq, 2, 2) \ - PROCESS_SIMD (pmovzxdq, 2, 2) \ - PROCESS_SIMD (psignb, 2, 3) \ - PROCESS_SIMD (psignw, 2, 3) \ - PROCESS_SIMD (psignd, 2, 3) \ - PROCESS_SIMD (packusdw, 2, 3) \ - PROCESS_SIMD (pcmpeqq, 2, 3) \ - PROCESS_SIMD (pcmpgtq, 2, 3) \ - PROCESS_SIMD (phaddw, 2, 3) \ - PROCESS_SIMD (phaddd, 2, 3) \ - PROCESS_SIMD (phaddsw, 2, 3) \ - PROCESS_SIMD (phsubw, 2, 3) \ - PROCESS_SIMD (phsubd, 2, 3) \ - PROCESS_SIMD (phsubsw, 2, 3) \ - PROCESS_SIMD (pmaddubsw, 2, 3) \ - PROCESS_SIMD (pmaxsb, 2, 3) \ - PROCESS_SIMD (pmaxsd, 2, 3) \ - PROCESS_SIMD (pmaxuw, 2, 3) \ - PROCESS_SIMD (pmaxud, 2, 3) \ - PROCESS_SIMD (pminsb, 2, 3) \ - PROCESS_SIMD (pminsd, 2, 3) \ - PROCESS_SIMD (pminud, 2, 3) \ - PROCESS_SIMD (pminuw, 2, 3) \ - PROCESS_SIMD (pmuldq, 2, 3) \ - PROCESS_SIMD (pmulhrsw, 2, 3) \ - PROCESS_SIMD (pmulld, 2, 3) \ - PROCESS_SIMD (pshufb, 2, 3) \ - PROCESS_SIMD (pshufhw, 3, 3) \ - PROCESS_SIMD (pshuflw, 3, 3) \ - PROCESS_SIMD (pmovmskb, 2, 2) \ - PROCESS_SIMD_FLOAT (add, 2, 3) \ - PROCESS_SIMD_FLOAT (and, 2, 3) \ - PROCESS_SIMD_FLOAT (andn, 2, 3) \ - PROCESS_SIMD (blendps, 3, 4) \ - PROCESS_SIMD (blendpd, 3, 4) \ - PROCESS_SIMD_FLOAT (div, 2, 3) \ - PROCESS_SIMD (hsubps, 2, 3) \ - PROCESS_SIMD (hsubpd, 2, 3) \ - PROCESS_SIMD_FLOAT (max, 2, 3) \ - PROCESS_SIMD_FLOAT (min, 2, 3) \ - PROCESS_SIMD_FLOAT (mul, 2, 3) \ - PROCESS_SIMD_FLOAT (or, 2, 3) \ - PROCESS_SIMD_FLOAT (round, 3, 4) \ - PROCESS_SIMD_FLOAT (sub, 2, 3) \ - PROCESS_SIMD_FLOAT (xor, 2, 3) \ - PROCESS_SIMD_FLOAT_SINGLE (rcp, 2, 2) \ - PROCESS_SIMD_FLOAT_SINGLE (rsqrt, 2, 2) \ - PROCESS_SIMD_FLOAT (sqrt, 2, 2) \ - PROCESS_SIMD_FLOAT (cmp, 3, 4) \ - PROCESS_SIMD_FLOAT (shuf, 3, 4) \ - PROCESS_INSTRUCTION (vcvtph2ps, 2) \ - PROCESS_INSTRUCTION (vcvtps2ph, 3) \ - PROCESS_INSTRUCTION (vzeroall, 0) \ - PROCESS_INSTRUCTION (vzeroupper, 0) \ - PROCESS_INSTRUCTION (ldmxcsr, 1) \ - PROCESS_INSTRUCTION (vldmxcsr, 1) \ - PROCESS_INSTRUCTION (stmxcsr, 1) \ - PROCESS_INSTRUCTION (vstmxcsr, 1) \ - PROCESS_INSTRUCTION (fxsave, 1) \ - PROCESS_INSTRUCTION (fxrstor, 1) \ - PROCESS_INSTRUCTION (vmaskmovps, 3) \ - PROCESS_INSTRUCTION (vmaskmovpd, 3) \ - PROCESS_SIMD (pinsrb, 3, 4) \ - PROCESS_SIMD (pinsrd, 3, 4) \ - PROCESS_SIMD (pinsrq, 3, 4) \ - PROCESS_SIMD (pextrb, 3, 3) \ - PROCESS_SIMD (pextrd, 3, 3) \ - PROCESS_SIMD (pextrq, 3, 3) \ - PROCESS_INSTRUCTION (crc32, 2) \ - PROCESS_INSTRUCTION (vgatherdd, 3) \ - PROCESS_INSTRUCTION (vgatherqd, 3) \ - PROCESS_INSTRUCTION (vgatherdq, 3) \ - PROCESS_INSTRUCTION (vgatherqq, 3) \ - PROCESS_INSTRUCTION (vgatherdps, 3) \ - PROCESS_INSTRUCTION (vgatherqps, 3) \ - PROCESS_INSTRUCTION (vgatherdpd, 3) \ - PROCESS_INSTRUCTION (vgatherqpd, 3) \ - PROCESS_INSTRUCTION (andn, 3) \ - PROCESS_INSTRUCTION (bextr, 3) \ - PROCESS_INSTRUCTION (blsi, 2) \ - PROCESS_INSTRUCTION (blsmsk, 2) \ - PROCESS_INSTRUCTION (blsr, 2) \ - PROCESS_INSTRUCTION (bzhi, 3) \ - PROCESS_INSTRUCTION (lzcnt, 2) \ - PROCESS_INSTRUCTION (popcnt, 2) \ - PROCESS_INSTRUCTION (mulx, 3) \ - PROCESS_INSTRUCTION (pdep, 3) \ - PROCESS_INSTRUCTION (pext, 3) \ - PROCESS_INSTRUCTION (rorx, 3) \ - PROCESS_INSTRUCTION (sarx, 3) \ - PROCESS_INSTRUCTION (shlx, 3) \ - PROCESS_INSTRUCTION (shrx, 3) \ - PROCESS_INSTRUCTION (tzcnt, 2) \ - PROCESS_INSTRUCTION (vpcmov, 4) \ + PROCESS_INSTRUCTION (imul1, R, 1) \ + PROCESS_INSTRUCTION (imul2, BR, 2) \ + PROCESS_INSTRUCTION (imul3, WRR, 3) \ + PROCESS_SIMD (movdqa, WR, 2, WR, 2) \ + PROCESS_SIMD (movdqu, WR, 2, WR, 2) \ + PROCESS_SIMD (lddqu, WR, 2, WR, 2) \ + PROCESS_SIMD (palignr, BRR, 3, WRRR, 4) \ + PROCESS_SIMD (packsswb, BR, 2, WRR, 3) \ + PROCESS_SIMD (packssdw, BR, 2, WRR, 3) \ + PROCESS_SIMD (packuswb, BR, 2, WRR, 3) \ + PROCESS_SIMD (pand, BR, 2, WRR, 3) \ + PROCESS_SIMD (pandn, BR, 2, WRR, 3) \ + PROCESS_SIMD (por, BR, 2, WRR, 3) \ + PROCESS_SIMD (pxor, BR, 2, WRR, 3) \ + PROCESS_SIMD (pavgb, BR, 2, WRR, 3) \ + PROCESS_SIMD (pavgw, BR, 2, WRR, 3) \ + PROCESS_SIMD (paddb, BR, 2, WRR, 3) \ + PROCESS_SIMD (paddw, BR, 2, WRR, 3) \ + PROCESS_SIMD (paddd, BR, 2, WRR, 3) \ + PROCESS_SIMD (paddq, BR, 2, WRR, 3) \ + PROCESS_SIMD (paddsb, BR, 2, WRR, 3) \ + PROCESS_SIMD (paddsw, BR, 2, WRR, 3) \ + PROCESS_SIMD (paddusb, BR, 2, WRR, 3) \ + PROCESS_SIMD (paddusw, BR, 2, WRR, 3) \ + PROCESS_SIMD (pcmpeqb, BR, 2, WRR, 3) \ + PROCESS_SIMD (pcmpeqw, BR, 2, WRR, 3) \ + PROCESS_SIMD (pcmpeqd, BR, 2, WRR, 3) \ + PROCESS_SIMD (pcmpgtb, BR, 2, WRR, 3) \ + PROCESS_SIMD (pcmpgtw, BR, 2, WRR, 3) \ + PROCESS_SIMD (pcmpgtd, BR, 2, WRR, 3) \ + PROCESS_SIMD (pmaddwd, BR, 2, WRR, 3) \ + PROCESS_SIMD (pmaxsw, BR, 2, WRR, 3) \ + PROCESS_SIMD (pmaxub, BR, 2, WRR, 3) \ + PROCESS_SIMD (pminsw, BR, 2, WRR, 3) \ + PROCESS_SIMD (pminub, BR, 2, WRR, 3) \ + PROCESS_SIMD (pmulhuw, BR, 2, WRR, 3) \ + PROCESS_SIMD (pmulhw, BR, 2, WRR, 3) \ + PROCESS_SIMD (pmullw, BR, 2, WRR, 3) \ + PROCESS_SIMD (pmuludq, BR, 2, WRR, 3) \ + PROCESS_SIMD (psadbw, BR, 2, WRR, 3) \ + PROCESS_SIMD (psubb, BR, 2, WRR, 3) \ + PROCESS_SIMD (psubw, BR, 2, WRR, 3) \ + PROCESS_SIMD (psubd, BR, 2, WRR, 3) \ + PROCESS_SIMD (psubq, BR, 2, WRR, 3) \ + PROCESS_SIMD (psubsb, BR, 2, WRR, 3) \ + PROCESS_SIMD (psubsw, BR, 2, WRR, 3) \ + PROCESS_SIMD (psubusb, BR, 2, WRR, 3) \ + PROCESS_SIMD (psubusw, BR, 2, WRR, 3) \ + PROCESS_SIMD (punpckhbw, BR, 2, WRR, 3) \ + PROCESS_SIMD (punpckhwd, BR, 2, WRR, 3) \ + PROCESS_SIMD (punpckhdq, BR, 2, WRR, 3) \ + PROCESS_SIMD (punpcklbw, BR, 2, WRR, 3) \ + PROCESS_SIMD (punpcklwd, BR, 2, WRR, 3) \ + PROCESS_SIMD (punpckldq, BR, 2, WRR, 3) \ + PROCESS_SIMD (psllw, BR, 2, WRR, 3) \ + PROCESS_SIMD (pslld, BR, 2, WRR, 3) \ + PROCESS_SIMD (psllq, BR, 2, WRR, 3) \ + PROCESS_SIMD (psrlw, BR, 2, WRR, 3) \ + PROCESS_SIMD (psrld, BR, 2, WRR, 3) \ + PROCESS_SIMD (psrlq, BR, 2, WRR, 3) \ + PROCESS_SIMD (psraw, BR, 2, WRR, 3) \ + PROCESS_SIMD (psrad, BR, 2, WRR, 3) \ + PROCESS_SIMD (pinsrw, BRR, 3, WRRR, 4) \ + PROCESS_SIMD (pextrw, BRR, 3, WRRR, 3) \ + PROCESS_SIMD (pabsb, WR, 2, WR, 2) \ + PROCESS_SIMD (pabsw, WR, 2, WR, 2) \ + PROCESS_SIMD (pabsd, WR, 2, WR, 2) \ + PROCESS_SIMD (ptest, WR, 2, WR, 2) \ + PROCESS_SIMD (phminposuw, WR, 2, WR, 2) \ + PROCESS_SIMD (pmovsxbw, WR, 2, WR, 2) \ + PROCESS_SIMD (pmovzxbw, WR, 2, WR, 2) \ + PROCESS_SIMD (pmovsxbd, WR, 2, WR, 2) \ + PROCESS_SIMD (pmovzxbd, WR, 2, WR, 2) \ + PROCESS_SIMD (pmovsxbq, WR, 2, WR, 2) \ + PROCESS_SIMD (pmovzxbq, WR, 2, WR, 2) \ + PROCESS_SIMD (pmovsxwd, WR, 2, WR, 2) \ + PROCESS_SIMD (pmovzxwd, WR, 2, WR, 2) \ + PROCESS_SIMD (pmovsxwq, WR, 2, WR, 2) \ + PROCESS_SIMD (pmovzxwq, WR, 2, WR, 2) \ + PROCESS_SIMD (pmovsxdq, WR, 2, WR, 2) \ + PROCESS_SIMD (pmovzxdq, WR, 2, WR, 2) \ + PROCESS_SIMD (psignb, BR, 2, WRR, 3) \ + PROCESS_SIMD (psignw, BR, 2, WRR, 3) \ + PROCESS_SIMD (psignd, BR, 2, WRR, 3) \ + PROCESS_SIMD (packusdw, BR, 2, WRR, 3) \ + PROCESS_SIMD (pcmpeqq, BR, 2, WRR, 3) \ + PROCESS_SIMD (pcmpgtq, BR, 2, WRR, 3) \ + PROCESS_SIMD (phaddw, BR, 2, WRR, 3) \ + PROCESS_SIMD (phaddd, BR, 2, WRR, 3) \ + PROCESS_SIMD (phaddsw, BR, 2, WRR, 3) \ + PROCESS_SIMD (phsubw, BR, 2, WRR, 3) \ + PROCESS_SIMD (phsubd, BR, 2, WRR, 3) \ + PROCESS_SIMD (phsubsw, BR, 2, WRR, 3) \ + PROCESS_SIMD (pmaddubsw, BR, 2, WRR, 3) \ + PROCESS_SIMD (pmaxsb, BR, 2, WRR, 3) \ + PROCESS_SIMD (pmaxsd, BR, 2, WRR, 3) \ + PROCESS_SIMD (pmaxuw, BR, 2, WRR, 3) \ + PROCESS_SIMD (pmaxud, BR, 2, WRR, 3) \ + PROCESS_SIMD (pminsb, BR, 2, WRR, 3) \ + PROCESS_SIMD (pminsd, BR, 2, WRR, 3) \ + PROCESS_SIMD (pminud, BR, 2, WRR, 3) \ + PROCESS_SIMD (pminuw, BR, 2, WRR, 3) \ + PROCESS_SIMD (pmuldq, BR, 2, WRR, 3) \ + PROCESS_SIMD (pmulhrsw, BR, 2, WRR, 3) \ + PROCESS_SIMD (pmulld, BR, 2, WRR, 3) \ + PROCESS_SIMD (pshufb, BR, 2, WRR, 3) \ + PROCESS_SIMD (pshufhw, WRR, 3, WRR, 3) \ + PROCESS_SIMD (pshuflw, WRR, 3, WRR, 3) \ + PROCESS_SIMD (pmovmskb, WR, 2, WR, 2) \ + PROCESS_SIMD_FLOAT (add, BR, 2, WRR, 3) \ + PROCESS_SIMD_FLOAT (and, BR, 2, WRR, 3) \ + PROCESS_SIMD_FLOAT (andn, BR, 2, WRR, 3) \ + PROCESS_SIMD (blendps, BRR, 3, WRRR, 4) \ + PROCESS_SIMD (blendpd, BRR, 3, WRRR, 4) \ + PROCESS_SIMD_FLOAT (div, BR, 2, WRR, 3) \ + PROCESS_SIMD (hsubps, BR, 2, WRR, 3) \ + PROCESS_SIMD (hsubpd, BR, 2, WRR, 3) \ + PROCESS_SIMD_FLOAT (max, BR, 2, WRR, 3) \ + PROCESS_SIMD_FLOAT (min, BR, 2, WRR, 3) \ + PROCESS_SIMD_FLOAT (mul, BR, 2, WRR, 3) \ + PROCESS_SIMD_FLOAT (or, BR, 2, WRR, 3) \ + PROCESS_SIMD_FLOAT (round, BRR, 3, WRRR, 4) \ + PROCESS_SIMD_FLOAT (sub, BR, 2, WRR, 3) \ + PROCESS_SIMD_FLOAT (xor, BR, 2, WRR, 3) \ + PROCESS_SIMD_FLOAT_SINGLE (rcp, WR, 2, WR, 2) \ + PROCESS_SIMD_FLOAT_SINGLE (rsqrt, WR, 2, WR, 2) \ + PROCESS_SIMD_FLOAT (sqrt, WR, 2, WR, 2) \ + PROCESS_SIMD_FLOAT (cmp, BRR, 3, WRRR, 4) \ + PROCESS_SIMD_FLOAT (shuf, BRR, 3, WRRR, 4) \ + PROCESS_INSTRUCTION (vcvtph2ps, WR, 2) \ + PROCESS_INSTRUCTION (vcvtps2ph, WRR, 3) \ + PROCESS_INSTRUCTION (vzeroall, NA, 0) \ + PROCESS_INSTRUCTION (vzeroupper, NA, 0) \ + PROCESS_INSTRUCTION (ldmxcsr, R, 1) \ + PROCESS_INSTRUCTION (vldmxcsr, R, 1) \ + PROCESS_INSTRUCTION (stmxcsr, W, 1) \ + PROCESS_INSTRUCTION (vstmxcsr, W, 1) \ + PROCESS_INSTRUCTION (fxsave, W, 1) \ + PROCESS_INSTRUCTION (fxrstor, W, 1) \ + PROCESS_INSTRUCTION (vmaskmovps, WRR, 3) \ + PROCESS_INSTRUCTION (vmaskmovpd, WRR, 3) \ + PROCESS_SIMD (pinsrb, BRR, 3, WRRR, 4) \ + PROCESS_SIMD (pinsrd, BRR, 3, WRRR, 4) \ + PROCESS_SIMD (pinsrq, BRR, 3, WRRR, 4) \ + PROCESS_SIMD (pextrb, BRR, 3, WRRR, 3) \ + PROCESS_SIMD (pextrd, BRR, 3, WRRR, 3) \ + PROCESS_SIMD (pextrq, BRR, 3, WRRR, 3) \ + PROCESS_INSTRUCTION (crc32, BR, 2) \ + PROCESS_INSTRUCTION (vgatherdd, BRB, 3) \ + PROCESS_INSTRUCTION (vgatherqd, BRB, 3) \ + PROCESS_INSTRUCTION (vgatherdq, BRB, 3) \ + PROCESS_INSTRUCTION (vgatherqq, BRB, 3) \ + PROCESS_INSTRUCTION (vgatherdps, BRB, 3) \ + PROCESS_INSTRUCTION (vgatherqps, BRB, 3) \ + PROCESS_INSTRUCTION (vgatherdpd, BRB, 3) \ + PROCESS_INSTRUCTION (vgatherqpd, BRB, 3) \ + PROCESS_INSTRUCTION (andn, WRR, 3) \ + PROCESS_INSTRUCTION (bextr, WRR, 3) \ + PROCESS_INSTRUCTION (blsi, WR, 2) \ + PROCESS_INSTRUCTION (blsmsk, WR, 2) \ + PROCESS_INSTRUCTION (blsr, WR, 2) \ + PROCESS_INSTRUCTION (bzhi, WRR, 3) \ + PROCESS_INSTRUCTION (lzcnt, WR, 2) \ + PROCESS_INSTRUCTION (popcnt, WR, 2) \ + PROCESS_INSTRUCTION (mulx, WRR, 3) \ + PROCESS_INSTRUCTION (pdep, WRR, 3) \ + PROCESS_INSTRUCTION (pext, WRR, 3) \ + PROCESS_INSTRUCTION (rorx, WRR, 3) \ + PROCESS_INSTRUCTION (sarx, WRR, 3) \ + PROCESS_INSTRUCTION (shlx, WRR, 3) \ + PROCESS_INSTRUCTION (shrx, WRR, 3) \ + PROCESS_INSTRUCTION (tzcnt, WR, 2) \ + PROCESS_INSTRUCTION (vpcmov, WRRR, 4) \ PROCESS_XOP_COMPARE (b) \ PROCESS_XOP_COMPARE (w) \ PROCESS_XOP_COMPARE (d) \ @@ -573,7 +589,7 @@ enum { I_none, -#define PROCESS_INSTRUCTION(name, n_ops) \ +#define PROCESS_INSTRUCTION(name, rwinfo, n_ops) \ I_##name##__serial, ALL_INSTRUCTIONS @@ -585,12 +601,18 @@ enum (((instruction) >> 6) & 7) #define GET_SERIAL(instruction) \ - (((instruction) >> 9)) + (((instruction) >> 17)) + +#define OP_READ(instruction, op) \ + ((((instruction) >> (9 + (op) * 2))) & 0x01) + +#define OP_WRITTEN(instruction, op) \ + ((((instruction) >> (9 + (op) * 2))) & 0x02) typedef enum { -#define PROCESS_INSTRUCTION(name, n_ops) \ - I_##name = (I_##name##__serial << 9) | (n_ops << 6) | OP_INST, +#define PROCESS_INSTRUCTION(name, rw, n_ops) \ + I_##name = (I_##name##__serial << 17) | ((rw) << 9) | ((n_ops) << 6) | OP_INST, ALL_INSTRUCTIONS #undef PROCESS_INSTRUCTION |