Overload all the simple binary functions.

All these functions have two versions in old platform,
which are XXX and I64XXX. The on BDW, we never need
the I64XXX version because the platform supports the
long binary operation.

Signed-off-by: Junyan He <junyan.he@linux.intel.com>
Reviewed-by: Zhigang Gong <zhigang.gong@linux.intel.com>

4 files changed, 41 insertions, 12 deletions

diff --git a/backend/src/backend/gen8_context.cpp b/backend/src/backend/gen8_context.cpp
index d9eb6bf8..cffb10d9 100644
--- a/backend/src/backend/gen8_context.cpp
+++ b/backend/src/backend/gen8_context.cpp
@@ -71,6 +71,33 @@ namespace gbe
     }
   }
 
+  void Gen8Context::emitBinaryInstruction(const SelectionInstruction &insn) {
+    switch (insn.opcode) {
+      case SEL_OP_SEL_INT64:
+      case SEL_OP_I64AND:
+      case SEL_OP_I64OR:
+      case SEL_OP_I64XOR:
+        /* Should never come to here, just use the common OPCODE. */
+        GBE_ASSERT(0);
+        break;
+      default:
+        GenContext::emitBinaryInstruction(insn);
+    }
+  }
+
+  void Gen8Context::emitBinaryWithTempInstruction(const SelectionInstruction &insn)
+  {
+    switch (insn.opcode) {
+      case SEL_OP_I64ADD:
+      case SEL_OP_I64SUB:
+        /* Should never come to here, just use the common OPCODE. */
+        GBE_ASSERT(0);
+        break;
+      default:
+        GenContext::emitBinaryWithTempInstruction(insn);
+    }
+  }
+
   void Gen8Context::packLongVec(GenRegister unpacked, GenRegister packed, uint32_t simd)
   {
     GBE_ASSERT(packed.subnr == 0);
diff --git a/backend/src/backend/gen8_context.hpp b/backend/src/backend/gen8_context.hpp
index a3c3aff6..54cc29d7 100644
--- a/backend/src/backend/gen8_context.hpp
+++ b/backend/src/backend/gen8_context.hpp
@@ -50,6 +50,8 @@ namespace gbe
 
     virtual void emitUnaryInstruction(const SelectionInstruction &insn);
     virtual void emitUnaryWithTempInstruction(const SelectionInstruction &insn);
+    virtual void emitBinaryInstruction(const SelectionInstruction &insn);
+    virtual void emitBinaryWithTempInstruction(const SelectionInstruction &insn);
     virtual void emitWrite64Instruction(const SelectionInstruction &insn);
     virtual void emitRead64Instruction(const SelectionInstruction &insn);
   protected:
diff --git a/backend/src/backend/gen_context.hpp b/backend/src/backend/gen_context.hpp
index 43d4e75b..3593d66b 100644
--- a/backend/src/backend/gen_context.hpp
+++ b/backend/src/backend/gen_context.hpp
@@ -126,8 +126,8 @@ namespace gbe
     void emitLabelInstruction(const SelectionInstruction &insn);
     virtual void emitUnaryInstruction(const SelectionInstruction &insn);
     virtual void emitUnaryWithTempInstruction(const SelectionInstruction &insn);
-    void emitBinaryInstruction(const SelectionInstruction &insn);
-    void emitBinaryWithTempInstruction(const SelectionInstruction &insn);
+    virtual void emitBinaryInstruction(const SelectionInstruction &insn);
+    virtual void emitBinaryWithTempInstruction(const SelectionInstruction &insn);
     void emitTernaryInstruction(const SelectionInstruction &insn);
     void emitI64MULHIInstruction(const SelectionInstruction &insn);
     void emitI64MADSATInstruction(const SelectionInstruction &insn);
diff --git a/backend/src/backend/gen_insn_selection.cpp b/backend/src/backend/gen_insn_selection.cpp
index 1dcdc41e..ca9d62c2 100644
--- a/backend/src/backend/gen_insn_selection.cpp
+++ b/backend/src/backend/gen_insn_selection.cpp
@@ -2255,14 +2255,14 @@ namespace gbe
 
       switch (opcode) {
         case OP_ADD:
-          if (type == Type::TYPE_U64 || type == Type::TYPE_S64) {
+          if ((type == Type::TYPE_U64 || type == Type::TYPE_S64) && !sel.hasLongType()) {
             GenRegister t = sel.selReg(sel.reg(RegisterFamily::FAMILY_QWORD), Type::TYPE_S64);
             sel.I64ADD(dst, src0, src1, t);
           } else
             sel.ADD(dst, src0, src1);
           break;
         case OP_ADDSAT:
-          if (type == Type::TYPE_U64 || type == Type::TYPE_S64) {
+          if ((type == Type::TYPE_U64 || type == Type::TYPE_S64) && !sel.hasLongType()) {
             GenRegister tmp[5];
             for(int i=0; i<5; i++) {
               tmp[i] = sel.selReg(sel.reg(FAMILY_DWORD));
@@ -2281,32 +2281,32 @@ namespace gbe
           sel.pop();
           break;
         case OP_XOR:
-          if (type == Type::TYPE_U64 || type == Type::TYPE_S64)
+          if ((type == Type::TYPE_U64 || type == Type::TYPE_S64) && !sel.hasLongType())
             sel.I64XOR(dst, src0, src1);
           else
             sel.XOR(dst, src0, src1);
           break;
         case OP_OR:
-          if (type == Type::TYPE_U64 || type == Type::TYPE_S64)
+          if ((type == Type::TYPE_U64 || type == Type::TYPE_S64) && !sel.hasLongType())
             sel.I64OR(dst, src0, src1);
           else
             sel.OR(dst, src0, src1);
           break;
         case OP_AND:
-          if (type == Type::TYPE_U64 || type == Type::TYPE_S64)
+          if ((type == Type::TYPE_U64 || type == Type::TYPE_S64) && !sel.hasLongType())
             sel.I64AND(dst, src0, src1);
           else
             sel.AND(dst, src0, src1);
           break;
         case OP_SUB:
-          if (type == Type::TYPE_U64 || type == Type::TYPE_S64) {
+          if ((type == Type::TYPE_U64 || type == Type::TYPE_S64) && !sel.hasLongType()) {
             GenRegister t = sel.selReg(sel.reg(RegisterFamily::FAMILY_QWORD), Type::TYPE_S64);
             sel.I64SUB(dst, src0, src1, t);
           } else
             sel.ADD(dst, src0, GenRegister::negate(src1));
           break;
         case OP_SUBSAT:
-          if (type == Type::TYPE_U64 || type == Type::TYPE_S64) {
+          if ((type == Type::TYPE_U64 || type == Type::TYPE_S64) && !sel.hasLongType()) {
             GenRegister tmp[5];
             for(int i=0; i<5; i++) {
               tmp[i] = sel.selReg(sel.reg(FAMILY_DWORD));
@@ -2325,7 +2325,7 @@ namespace gbe
           sel.pop();
           break;
         case OP_SHL:
-          if (type == TYPE_S64 || type == TYPE_U64) {
+          if ((type == Type::TYPE_U64 || type == Type::TYPE_S64) && !sel.hasLongType()) {
             GenRegister tmp[6];
             for(int i = 0; i < 6; i ++)
               tmp[i] = sel.selReg(sel.reg(FAMILY_DWORD));
@@ -2338,7 +2338,7 @@ namespace gbe
             sel.SHL(dst, src0, src1);
           break;
         case OP_SHR:
-          if (type == TYPE_S64 || type == TYPE_U64) {
+          if ((type == Type::TYPE_U64 || type == Type::TYPE_S64) && !sel.hasLongType()) {
             GenRegister tmp[6];
             for(int i = 0; i < 6; i ++)
               tmp[i] = sel.selReg(sel.reg(FAMILY_DWORD));
@@ -2351,7 +2351,7 @@ namespace gbe
             sel.SHR(dst, src0, src1);
           break;
         case OP_ASR:
-          if (type == TYPE_S64 || type == TYPE_U64) {
+          if ((type == Type::TYPE_U64 || type == Type::TYPE_S64) && !sel.hasLongType()) {
             GenRegister tmp[6];
             for(int i = 0; i < 6; i ++)
               tmp[i] = sel.selReg(sel.reg(FAMILY_DWORD));