Add PackLong and UnpackLong functions

Because there is no support for HStride = 8, when we do
the bitcast for u8 to u64 or u64 to u8, we need to pack/unpack
long into two DWords before mov. We need to add these two
assist functions here.

Signed-off-by: Junyan He <junyan.he@linux.intel.com>
Reviewed-by: Zhigang Gong <zhigang.gong@linux.intel.com>

7 files changed, 51 insertions, 0 deletions

diff --git a/backend/src/backend/gen8_context.cpp b/backend/src/backend/gen8_context.cpp
index bbfec961..fca4f05d 100644
--- a/backend/src/backend/gen8_context.cpp
+++ b/backend/src/backend/gen8_context.cpp
@@ -702,4 +702,22 @@ namespace gbe
 
     p->UNTYPED_WRITE(addr, bti, elemNum*2);
   }
+
+  void Gen8Context::emitPackLongInstruction(const SelectionInstruction &insn) {
+    const GenRegister src = ra->genReg(insn.src(0));
+    const GenRegister dst = ra->genReg(insn.dst(0));
+
+    /* Scalar register need not to convert. */
+    GBE_ASSERT(dst.hstride != GEN_HORIZONTAL_STRIDE_0 && src.hstride != GEN_HORIZONTAL_STRIDE_0);
+    this->packLongVec(src, dst, p->curr.execWidth);
+  }
+
+  void Gen8Context::emitUnpackLongInstruction(const SelectionInstruction &insn) {
+    const GenRegister src = ra->genReg(insn.src(0));
+    const GenRegister dst = ra->genReg(insn.dst(0));
+
+    /* Scalar register need not to convert. */
+    GBE_ASSERT(dst.hstride != GEN_HORIZONTAL_STRIDE_0 && src.hstride != GEN_HORIZONTAL_STRIDE_0);
+    this->unpackLongVec(src, dst, p->curr.execWidth);
+  }
 }
diff --git a/backend/src/backend/gen8_context.hpp b/backend/src/backend/gen8_context.hpp
index d5932253..a047990a 100644
--- a/backend/src/backend/gen8_context.hpp
+++ b/backend/src/backend/gen8_context.hpp
@@ -68,6 +68,9 @@ namespace gbe
     virtual void emitI64MULInstruction(const SelectionInstruction &insn);
     virtual void emitI64DIVREMInstruction(const SelectionInstruction &insn);
 
+    virtual void emitPackLongInstruction(const SelectionInstruction &insn);
+    virtual void emitUnpackLongInstruction(const SelectionInstruction &insn);
+
   protected:
     virtual GenEncoder* generateEncoder(void) {
       return GBE_NEW(Gen8Encoder, this->simdWidth, 8, deviceID);
diff --git a/backend/src/backend/gen_context.cpp b/backend/src/backend/gen_context.cpp
index 5b303c7c..f8748ad3 100644
--- a/backend/src/backend/gen_context.cpp
+++ b/backend/src/backend/gen_context.cpp
@@ -1739,6 +1739,14 @@ namespace gbe
     p->pop();
   }
 
+  void GenContext::emitUnpackLongInstruction(const SelectionInstruction &insn) {
+    GBE_ASSERT(0);
+  }
+
+  void GenContext::emitPackLongInstruction(const SelectionInstruction &insn) {
+    GBE_ASSERT(0);
+  }
+
   void GenContext::emitDWordGatherInstruction(const SelectionInstruction &insn) {
     const GenRegister dst = ra->genReg(insn.dst(0));
     const GenRegister src = ra->genReg(insn.src(0));
diff --git a/backend/src/backend/gen_context.hpp b/backend/src/backend/gen_context.hpp
index e307d78d..c68e6cf1 100644
--- a/backend/src/backend/gen_context.hpp
+++ b/backend/src/backend/gen_context.hpp
@@ -157,6 +157,8 @@ namespace gbe
     void emitByteScatterInstruction(const SelectionInstruction &insn);
     void emitPackByteInstruction(const SelectionInstruction &insn);
     void emitUnpackByteInstruction(const SelectionInstruction &insn);
+    virtual void emitPackLongInstruction(const SelectionInstruction &insn);
+    virtual void emitUnpackLongInstruction(const SelectionInstruction &insn);
     void emitDWordGatherInstruction(const SelectionInstruction &insn);
     void emitSampleInstruction(const SelectionInstruction &insn);
     void emitTypedWriteInstruction(const SelectionInstruction &insn);
diff --git a/backend/src/backend/gen_insn_gen7_schedule_info.hxx b/backend/src/backend/gen_insn_gen7_schedule_info.hxx
index 8535b4a0..d0548201 100644
--- a/backend/src/backend/gen_insn_gen7_schedule_info.hxx
+++ b/backend/src/backend/gen_insn_gen7_schedule_info.hxx
@@ -32,6 +32,8 @@ DECL_GEN7_SCHEDULE(ByteScatter,     160,       1,        1)
 DECL_GEN7_SCHEDULE(DWordGather,     160,       1,        1)
 DECL_GEN7_SCHEDULE(PackByte,        40,        1,        1)
 DECL_GEN7_SCHEDULE(UnpackByte,      40,        1,        1)
+DECL_GEN7_SCHEDULE(PackLong,        40,        1,        1)
+DECL_GEN7_SCHEDULE(UnpackLong,      40,        1,        1)
 DECL_GEN7_SCHEDULE(Sample,          160,       1,        1)
 DECL_GEN7_SCHEDULE(TypedWrite,      80,        1,        1)
 DECL_GEN7_SCHEDULE(SpillReg,        20,        1,        1)
diff --git a/backend/src/backend/gen_insn_selection.cpp b/backend/src/backend/gen_insn_selection.cpp
index aeb5da38..5b336b29 100644
--- a/backend/src/backend/gen_insn_selection.cpp
+++ b/backend/src/backend/gen_insn_selection.cpp
@@ -594,6 +594,10 @@ namespace gbe
     void UNPACK_BYTE(const GenRegister *dst, const GenRegister src, uint32_t elemSize, uint32_t elemNum);
     /*! pack the charN to uint */
     void PACK_BYTE(const GenRegister dst, const GenRegister *src, uint32_t elemSize, uint32_t elemNum);
+    /*! Unpack the uint to charN */
+    void UNPACK_LONG(const GenRegister dst, const GenRegister src);
+    /*! pack the charN to uint */
+    void PACK_LONG(const GenRegister dst, const GenRegister src);
     /*! Extended math function (2 arguments) */
     void MATH(Reg dst, uint32_t function, Reg src0, Reg src1);
     /*! Extended math function (1 argument) */
@@ -1346,6 +1350,18 @@ namespace gbe
     insn->dst(0) = dst;
   }
 
+  void Selection::Opaque::UNPACK_LONG(const GenRegister dst, const GenRegister src) {
+    SelectionInstruction *insn = this->appendInsn(SEL_OP_UNPACK_LONG, 1, 1);
+    insn->src(0) = src;
+    insn->dst(0) = dst;
+  }
+
+  void Selection::Opaque::PACK_LONG(const GenRegister dst, const GenRegister src) {
+    SelectionInstruction *insn = this->appendInsn(SEL_OP_PACK_LONG, 1, 1);
+    insn->src(0) = src;
+    insn->dst(0) = dst;
+  }
+
   void Selection::Opaque::MATH(Reg dst, uint32_t function, Reg src0, Reg src1) {
     SelectionInstruction *insn = this->appendInsn(SEL_OP_MATH, 1, 2);
     insn->dst(0) = dst;
diff --git a/backend/src/backend/gen_insn_selection.hxx b/backend/src/backend/gen_insn_selection.hxx
index da8086e0..be1f7ec3 100644
--- a/backend/src/backend/gen_insn_selection.hxx
+++ b/backend/src/backend/gen_insn_selection.hxx
@@ -60,6 +60,8 @@ DECL_SELECTION_IR(BYTE_SCATTER, ByteScatterInstruction)
 DECL_SELECTION_IR(DWORD_GATHER, DWordGatherInstruction)
 DECL_SELECTION_IR(PACK_BYTE, PackByteInstruction)
 DECL_SELECTION_IR(UNPACK_BYTE, UnpackByteInstruction)
+DECL_SELECTION_IR(PACK_LONG, PackLongInstruction)
+DECL_SELECTION_IR(UNPACK_LONG, UnpackLongInstruction)
 DECL_SELECTION_IR(SAMPLE, SampleInstruction)
 DECL_SELECTION_IR(TYPED_WRITE, TypedWriteInstruction)
 DECL_SELECTION_IR(SPILL_REG, SpillRegInstruction)