diff options
| author | Ruiling Song <ruiling.song@intel.com> | 2015-01-28 15:07:58 +0800 |
|---|---|---|
| committer | Zhigang Gong <zhigang.gong@intel.com> | 2015-01-29 13:05:33 +0800 |
| commit | 5322f46ae5b13b64c09c18f423f82bccfeb23cca (patch) | |
| tree | 1c36c1e298c5f10bddda7f64b041ea0bee15d2c9 | |
| parent | 74a349403a88059b36e56760221f4f1b7d80c256 (diff) | |
libocl: Refine char/short abs() implementation.
We don't need to convert char/short to int when calling abs().
Signed-off-by: Ruiling Song <ruiling.song@intel.com>
Reviewed-by: Zhigang Gong <zhigang.gong@linux.intel.com>
| -rw-r--r-- | backend/src/backend/gen_insn_selection.cpp | 9 | ||||
| -rw-r--r-- | backend/src/libocl/tmpl/ocl_integer.tmpl.cl | 4 | ||||
| -rw-r--r-- | backend/src/llvm/llvm_gen_backend.cpp | 2 |
3 files changed, 7 insertions, 8 deletions
diff --git a/backend/src/backend/gen_insn_selection.cpp b/backend/src/backend/gen_insn_selection.cpp index d762848f..65842ff7 100644 --- a/backend/src/backend/gen_insn_selection.cpp +++ b/backend/src/backend/gen_insn_selection.cpp @@ -2071,13 +2071,10 @@ namespace gbe } switch (opcode) { case ir::OP_ABS: - if (insn.getType() == ir::TYPE_S32) { - const GenRegister src_ = GenRegister::retype(src, GEN_TYPE_D); - const GenRegister dst_ = GenRegister::retype(dst, GEN_TYPE_D); + { + const GenRegister src_ = GenRegister::retype(src, getGenType(insnType)); + const GenRegister dst_ = GenRegister::retype(dst, getGenType(insnType)); sel.MOV(dst_, GenRegister::abs(src_)); - } else { - GBE_ASSERT(insn.getType() == ir::TYPE_FLOAT); - sel.MOV(dst, GenRegister::abs(src)); } break; case ir::OP_MOV: diff --git a/backend/src/libocl/tmpl/ocl_integer.tmpl.cl b/backend/src/libocl/tmpl/ocl_integer.tmpl.cl index a5e1dbc1..4a06f15b 100644 --- a/backend/src/libocl/tmpl/ocl_integer.tmpl.cl +++ b/backend/src/libocl/tmpl/ocl_integer.tmpl.cl @@ -278,7 +278,9 @@ OVERLOADABLE ulong rhadd(ulong x, ulong y) { return __gen_ocl_rhadd(x, y); } -int __gen_ocl_abs(int x); +PURE CONST OVERLOADABLE char __gen_ocl_abs(char x); +PURE CONST OVERLOADABLE short __gen_ocl_abs(short x); +PURE CONST OVERLOADABLE int __gen_ocl_abs(int x); #define DEC(TYPE) OVERLOADABLE u##TYPE abs(TYPE x) { return (u##TYPE) __gen_ocl_abs(x); } DEC(int) DEC(short) diff --git a/backend/src/llvm/llvm_gen_backend.cpp b/backend/src/llvm/llvm_gen_backend.cpp index b9eaf56b..66a7e935 100644 --- a/backend/src/llvm/llvm_gen_backend.cpp +++ b/backend/src/llvm/llvm_gen_backend.cpp @@ -3434,7 +3434,7 @@ error: { const ir::Register src = this->getRegister(*AI); const ir::Register dst = this->getRegister(&I); - ctx.ALU1(ir::OP_ABS, ir::TYPE_S32, dst, src); + ctx.ALU1(ir::OP_ABS, getType(ctx, (*AI)->getType()), dst, src); break; } case GEN_OCL_SIMD_ALL: |