diff options
| author | Junyan He <junyan.he@linux.intel.com> | 2015-01-26 18:18:03 +0800 |
|---|---|---|
| committer | Zhigang Gong <zhigang.gong@intel.com> | 2015-01-28 12:45:14 +0800 |
| commit | 2757e2eeb6ca68bf2c725ed66cedb55c82ee6e90 (patch) | |
| tree | 4f2c3be7fcee58e38a220bd78aee66ab18ef6615 | |
| parent | 600d23b04e8be609fa5dcdc6ffcc0e383799cd40 (diff) | |
Fix the long bitcast post schedule bug.
The tmp registers are in wrong type of float, which will
cause the post schedule error.
Signed-off-by: Junyan He <junyan.he@linux.intel.com>
Reviewed-by: "Yang, Rong R" <rong.r.yang@intel.com>
Reviewed-by: Zhigang Gong <zhigang.gong@linux.intel.com>
| -rw-r--r-- | backend/src/backend/gen_insn_selection.cpp | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/backend/src/backend/gen_insn_selection.cpp b/backend/src/backend/gen_insn_selection.cpp index 628fa2f1..6aa7e0e9 100644 --- a/backend/src/backend/gen_insn_selection.cpp +++ b/backend/src/backend/gen_insn_selection.cpp @@ -3623,12 +3623,12 @@ namespace gbe GBE_ASSERT(isInt64); // Must relate to long and char conversion. if (narrowDst) { for (int i = 0; i < wideNum; i++) { - tmp[i] = sel.selReg(sel.reg(FAMILY_QWORD)); + tmp[i] = sel.selReg(sel.reg(FAMILY_QWORD), ir::TYPE_U64); sel.UNPACK_LONG(tmp[i], sel.selReg(insn.getSrc(i), srcType)); } } else { for (int i = 0; i < wideNum; i++) { - tmp[i] = sel.selReg(sel.reg(FAMILY_QWORD)); + tmp[i] = sel.selReg(sel.reg(FAMILY_QWORD), ir::TYPE_U64); } } } |