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| author | Guo Yejun <yejun.guo@intel.com> | 2015-01-22 10:29:42 +0800 |
|---|---|---|
| committer | Zhigang Gong <zhigang.gong@intel.com> | 2015-01-23 11:59:29 +0800 |
| commit | 17073acc3e721deeafaa4aec5986017ebeaf85f1 (patch) | |
| tree | 7d817a0559ca4bf2dbe4bd0f30d88fc3e6632ecd | |
| parent | 5f502770395bc3bd24882e8cb6b21efc3942692c (diff) | |
correct the cache line size to be 64
the correct value of cache line size is 64 bytes, not 128.
Signed-off-by: Guo Yejun <yejun.guo@intel.com>
Reviewed-by: Zhigang Gong <zhigang.gong@linux.intel.com>
| -rw-r--r-- | src/cl_gen75_device.h | 2 | ||||
| -rw-r--r-- | src/cl_gen7_device.h | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/src/cl_gen75_device.h b/src/cl_gen75_device.h index 8cf2dcd5..43f6e8ff 100644 --- a/src/cl_gen75_device.h +++ b/src/cl_gen75_device.h @@ -20,7 +20,7 @@ /* Common fields for both SNB devices (either GT1 or GT2) */ .max_parameter_size = 1024, -.global_mem_cache_line_size = 128, /* XXX */ +.global_mem_cache_line_size = 64, /* XXX */ .global_mem_cache_size = 8 << 10, /* XXX */ .local_mem_type = CL_GLOBAL, .local_mem_size = 64 << 10, diff --git a/src/cl_gen7_device.h b/src/cl_gen7_device.h index 6857f8a6..4ad5d96d 100644 --- a/src/cl_gen7_device.h +++ b/src/cl_gen7_device.h @@ -19,7 +19,7 @@ /* Common fields for both IVB devices (either GT1 or GT2) */ .max_parameter_size = 1024, -.global_mem_cache_line_size = 128, /* XXX */ +.global_mem_cache_line_size = 64, /* XXX */ .global_mem_cache_size = 8 << 10, /* XXX */ .local_mem_type = CL_GLOBAL, .local_mem_size = 64 << 10, |