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; options:
; VERT: new compiler
@in(r1.x) in0
@in(r1.y) in1
@in(r1.z) in2
@in(r1.w) in3
@out(r0.x) out0
@out(r0.y) out1
@out(r0.z) out2
@out(r0.w) out3
@out(r1.x) out4
@out(r1.y) out5
@out(r1.z) out6
@out(r1.w) out7
(sy)(ss)mov.f32f32 r0.x, c0.x
mov.f32f32 r0.y, c0.x
mul.f r0.z, c2.w, r1.x
mul.f r0.w, c2.z, r1.x
cmps.u.eq r0.x, r0.x, c6.y
cmps.u.eq r0.y, r0.y, c6.z
mad.f32 r0.z, c3.w, r1.y, r0.z
mad.f32 r0.w, c3.z, r1.y, r0.w
absneg.s r0.x, (neg)r0.x
absneg.s r0.y, (neg)r0.y
mad.f32 r0.z, c4.w, r1.z, r0.z
mad.f32 r0.w, c4.z, r1.z, r0.w
cov.s32f32 r0.x, r0.x
cov.s32f32 r0.y, r0.y
mad.f32 r0.z, c5.w, r1.w, r0.z
mad.f32 r2.x, c5.z, r1.w, r0.w
cmps.f.lt r0.x, r0.x, c6.x
mov.f32f32 r0.y, r0.y
(rpt1)nop
sel.b32 r0.x, c7.y, r0.x, c7.x
cmps.f.lt r0.y, r0.y, c6.x
mov.f32f32 r0.w, r0.z
mov.f32f32 r0.z, r2.x
mov.f32f32 r0.x, r0.x
mul.f r2.x, c2.y, r1.x
mul.f r1.x, c2.x, r1.x
mad.f32 r2.x, c3.y, r1.y, r2.x
sel.b32 r0.x, c7.z, r0.y, r0.x
mad.f32 r0.y, c4.y, r1.z, r2.x
mad.f32 r1.x, c3.x, r1.y, r1.x
mad.f32 r0.y, c5.y, r1.w, r0.y
mov.f32f32 r0.x, r0.x
mad.f32 r1.x, c4.x, r1.z, r1.x
mov.f32f32 r1.y, c8.y
mov.f32f32 r1.z, c8.y
cmps.f.eq r0.x, r0.x, c1.x
mov.f32f32 r0.y, r0.y
mad.f32 r2.x, c5.x, r1.w, r1.x
nop
absneg.s r0.x, (neg)r0.x
mov.f32f32 r1.x, c8.x
mov.f32f32 r1.w, c8.x
mov.f32f32 r2.y, c8.x
cmps.u.ne r0.x, r0.x, c6.x
mov.f32f32 r2.z, c8.y
mov.f32f32 r2.w, c8.x
mov.f32f32 r3.x, c8.y
sel.b32 r1.y, r1.z, r0.x, r1.y
sel.b32 r1.x, r1.w, r0.x, r1.x
sel.b32 r2.y, r2.z, r0.x, r2.y
sel.b32 r0.x, r2.w, r0.x, r3.x
mov.f32f32 r1.w, r1.y
mov.f32f32 r1.z, r1.x
mov.f32f32 r1.y, r2.y
mov.f32f32 r1.x, r0.x
mov.f32f32 r0.x, r2.x
end
nop
nop
nop
; VERT: outputs: r0.x (0:0) r1.x (5:20)
; VERT: inputs: r1.x (0:0,cm=f,il=8,b=0)
; VERT: 58 instructions, 0 half, 4 full
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