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path: root/drivers/gpu/drm/i915/display/intel_display_types.h
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Diffstat (limited to 'drivers/gpu/drm/i915/display/intel_display_types.h')
-rw-r--r--drivers/gpu/drm/i915/display/intel_display_types.h26
1 files changed, 5 insertions, 21 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index c9c6efadf8b4..60e15226a8cb 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -32,10 +32,10 @@
#include <linux/pwm.h>
#include <linux/sched/clock.h>
+#include <drm/dp/drm_dp_dual_mode_helper.h>
+#include <drm/dp/drm_dp_mst_helper.h>
#include <drm/drm_atomic.h>
#include <drm/drm_crtc.h>
-#include <drm/drm_dp_dual_mode_helper.h>
-#include <drm/drm_dp_mst_helper.h>
#include <drm/drm_dsc.h>
#include <drm/drm_encoder.h>
#include <drm/drm_fb_helper.h>
@@ -634,6 +634,9 @@ struct intel_plane_state {
struct intel_fb_view view;
+ /* Indicates if async flip is required */
+ bool do_async_flip;
+
/* Plane pxp decryption state */
bool decrypt;
@@ -1442,25 +1445,6 @@ struct intel_hdmi {
};
struct intel_dp_mst_encoder;
-/*
- * enum link_m_n_set:
- * When platform provides two set of M_N registers for dp, we can
- * program them and switch between them incase of DRRS.
- * But When only one such register is provided, we have to program the
- * required divider value on that registers itself based on the DRRS state.
- *
- * M1_N1 : Program dp_m_n on M1_N1 registers
- * dp_m2_n2 on M2_N2 registers (If supported)
- *
- * M2_N2 : Program dp_m2_n2 on M1_N1 registers
- * M2_N2 registers are not supported
- */
-
-enum link_m_n_set {
- /* Sets the m1_n1 and m2_n2 */
- M1_N1 = 0,
- M2_N2
-};
struct intel_dp_compliance_data {
unsigned long edid;