diff options
author | Patrice Mandin <pmandin@caramail.com> | 2008-08-28 18:01:19 +0200 |
---|---|---|
committer | Patrice Mandin <pmandin@caramail.com> | 2008-08-28 18:01:19 +0200 |
commit | 524acc2e2dfe886cb5ef82f37846f9d055ce431e (patch) | |
tree | 8cb60bbf308425cc2db0134540a15f99baf83874 | |
parent | 4fabe40a9318197cc59723e29e947c2209d6e0b4 (diff) |
wrong subchannel for notify, try with shader engine without success
-rw-r--r-- | tcl_init.c | 26 |
1 files changed, 21 insertions, 5 deletions
@@ -68,6 +68,9 @@ void tcl_init(void) SetSubchannel(NvSubImageBlit, NvImageBlit); SetSubchannel(NvSub3D, Nv3D); + BEGIN_RING(NvSub3D, NV34TCL_DMA_NOTIFY, 1); + OUT_RING(NvSyncNotify); + BEGIN_RING(NvSub3D, NV34TCL_DMA_TEXTURE0, 3); OUT_RING(NvDmaFB); /* beef0201 184 texture0 */ OUT_RING(NvDmaTT); /* beef0202 188 texture1 */ @@ -172,11 +175,11 @@ void tcl_init(void) # INST 0: MOVX R0 (TR0.xyzw), attrib.color + END 07bfef01 NV30TCL.FP_ACTIVE_PROGRAM = DMA0=TRUE | DMA1=FALSE | OFFSET=0x07bfef00 #endif - /*tcl_fp_color(); + tcl_fp_color(); BEGIN_RING(NvSub3D, NV34TCL_FP_CONTROL, 1); OUT_RING(0); BEGIN_RING(NvSub3D, NV34TCL_FP_REG_CONTROL, 1); - OUT_RING((1<<16)|4);*/ + OUT_RING((1<<16)|4); BEGIN_RING(NvSub3D, NV34TCL_TX_UNITS_ENABLE, 1); OUT_RING(0); @@ -318,8 +321,9 @@ void tcl_init(void) OUT_RING(0); BEGIN_RING(NvSub3D, NV34TCL_ENGINE, 1); - OUT_RING(NV34TCL_ENGINE_FIXED); + OUT_RING(0x13 /*NV34TCL_ENGINE_FIXED*/); +#if 0 BEGIN_RING(NvSub3D, NV34TCL_VIEWPORT_TRANSLATE_X, 4); OUT_RINGf(viewport_w * 1.0); OUT_RINGf(viewport_h * 1.0); @@ -330,6 +334,18 @@ void tcl_init(void) OUT_RINGf(viewport_h / -2.0); OUT_RINGf(0.5); OUT_RINGf(0.0); +#else + BEGIN_RING(NvSub3D, NV34TCL_VIEWPORT_TRANSLATE_X, 8); + OUT_RINGf(0.0); + OUT_RINGf(0.0); + OUT_RINGf(0.0); + OUT_RINGf(0.0); + + OUT_RINGf(1.0); + OUT_RINGf(1.0); + OUT_RINGf(1.0); + OUT_RINGf(0.0); +#endif BEGIN_RING(NvSub3D, NV34TCL_VP_CLIP_PLANES_ENABLE, 1); OUT_RING(0); @@ -360,12 +376,12 @@ void tcl_init(void) # INST 0: NOP (FL0.xxxx) + END 07bfef41 NV30TCL.FP_ACTIVE_PROGRAM = DMA0=TRUE | DMA1=FALSE | OFFSET=0x07bfef40 #endif - tcl_fp_nop(); + /*tcl_fp_nop(); BEGIN_RING(NvSub3D, NV34TCL_FP_CONTROL, 1); OUT_RING(0x40); BEGIN_RING(NvSub3D, NV34TCL_FP_REG_CONTROL, 1); - OUT_RING((1<<16)|4); + OUT_RING((1<<16)|4);*/ /*BEGIN_RING(NvSub3D, NV34TCL_CLEAR_DEPTH_VALUE, 2); OUT_RING(0); |