diff options
Diffstat (limited to 'src/CInt10Tbl.h')
| -rw-r--r-- | src/CInt10Tbl.h | 72 |
1 files changed, 37 insertions, 35 deletions
diff --git a/src/CInt10Tbl.h b/src/CInt10Tbl.h index d260474..99bc613 100644 --- a/src/CInt10Tbl.h +++ b/src/CInt10Tbl.h @@ -18,34 +18,36 @@ * <jason.lin@rdc.com.tw> */ + PORT_CONFIG *pPortConfig; MODE_INFO *pLCDTable; MODE_INFO *pVESATable; void *PCIDataStruct; +void *BiosInfoData; bool bCRTSUPPORT = false; bool bLCDSUPPORT = false; bool bDVISUPPORT = false; bool bTVSUPPORT = false; -/* common table for all VESA modes on display1 */ + void *Display1VESAModeInitRegs; -/* table pointers for VBIOS POST */ + void *POSTInItRegs; void *DDRII400Tbl; void *DDRII533Tbl; void *ExtendRegs2; -/* Display 1 registers table */ -/* Display 1 H total */ + + REG_OP HTotal1[] = { - {CR, 0xFF, 0x00,3}, /* [7:0] */ - {CR, BIT0, 0xAC,11}, /* [8] */ + {CR, 0xFF, 0x00,3}, + {CR, BIT0, 0xAC,11}, {NR,0x0,0x0,0x0} }; -/* Display 1 H DispEnd */ + REG_OP HDispEnd1[] = { {SR, BIT6+BIT5+BIT4, 0x33,0}, {CR, 0xFF, 0x01,3}, @@ -53,7 +55,7 @@ REG_OP HDispEnd1[] = { {NR,0x0,0x0,0x0} }; -/* Display 1 H BnkSt */ + REG_OP HBnkSt1[] = { {SR, BIT2+BIT1+BIT0, 0x34,0}, {CR, 0xFF, 0x02,3}, @@ -61,7 +63,7 @@ REG_OP HBnkSt1[] = { {NR,0x0,0x0,0x0} }; -/* Display 1 H BnkEnd */ + REG_OP HBnkEnd1[] = { {SR, BIT6+BIT5+BIT4, 0x34,0}, {CR, 0x1F, 0x03,3}, @@ -70,7 +72,7 @@ REG_OP HBnkEnd1[] = { {NR,0x0,0x0,0x0} }; -/* Display 1 H SyncSt */ + REG_OP HSyncSt1[] = { {SR, BIT2+BIT1+BIT0, 0x35,0}, {CR, 0xFF, 0x04,3}, @@ -78,7 +80,7 @@ REG_OP HSyncSt1[] = { {NR,0x0,0x0,0x0} }; -/* Display 1 H SyncEnd */ + REG_OP HSyncEnd1[] = { {SR, BIT6+BIT5+BIT4, 0x35,0}, {CR, 0x1F, 0x05,3}, @@ -86,7 +88,7 @@ REG_OP HSyncEnd1[] = { {NR,0x0,0x0,0x0} }; -/* Display 1 V Total */ + REG_OP VTotal1[] = { {CR, 0xFF, 0x06,0}, {CR, BIT0, 0x07,8}, @@ -95,7 +97,7 @@ REG_OP VTotal1[] = { {NR,0x0,0x0,0x0} }; -/* Display 1 V DispEnd */ + REG_OP VDispEnd1[] = { {CR, 0xFF, 0x12,0}, {CR, BIT1, 0x07,8}, @@ -104,7 +106,7 @@ REG_OP VDispEnd1[] = { {NR,0x0,0x0,0x0} }; -/* Display 1 V BnkSt */ + REG_OP VBnkSt1[] = { {CR, 0xFF, 0x15,0}, {CR, BIT3, 0x07,8}, @@ -113,14 +115,14 @@ REG_OP VBnkSt1[] = { {NR,0x0,0x0,0x0} }; -/* Display 1 V BnkEnd */ + REG_OP VBnkEnd1[] = { {CR, 0xFF, 0x16,0}, {CR, BIT4, 0xAE,8}, {NR,0x0,0x0,0x0} }; -/* Display 1 V SyncSt */ + REG_OP VSyncSt1[] = { {CR, 0xFF, 0x10,0}, {CR, BIT2, 0x07,8}, @@ -129,30 +131,30 @@ REG_OP VSyncSt1[] = { {NR,0x0,0x0,0x0} }; -/* Display 1 V SyncEnd */ + REG_OP VSyncEnd1[] = { {CR, BIT3+BIT2+BIT1+BIT0, 0x11,0}, {CR, BIT6+BIT5, 0xAE,4}, {NR,0x0,0x0,0x0} }; -/* Display 1 Pitch */ + REG_OP Pitch1[] = { {CR, 0xFF, 0x13,0}, {CR, 0x3F, 0xB0,8}, {NR,0x0,0x0,0x0} }; -/* Display 2 registers table */ -/* Display 2 H total */ + + REG_OP HTotal2[] = { - {CR, 0xFF, 0x23,3}, /* [7:0] */ - {CR, BIT0, 0x29,11}, /* [8] */ + {CR, 0xFF, 0x23,3}, + {CR, BIT0, 0x29,11}, {NR,0x0,0x0,0x0} }; -/* Display 2 H DispEnd */ + REG_OP HDispEnd2[] = { {SR, BIT6+BIT5+BIT4, 0x36,0}, {CR, 0xFF, 0x24,3}, @@ -160,7 +162,7 @@ REG_OP HDispEnd2[] = { {NR,0x0,0x0,0x0} }; -/* Display 2 H BnkSt */ + REG_OP HBnkSt2[] = { {SR, BIT2+BIT1+BIT0, 0x37,0}, {CR, 0xFF, 0x25,3}, @@ -168,7 +170,7 @@ REG_OP HBnkSt2[] = { {NR,0x0,0x0,0x0} }; -/* Display 2 H BnkEnd */ + REG_OP HBnkEnd2[] = { {SR, BIT6+BIT5+BIT4, 0x37,0}, {CR, 0x1F, 0x26,3}, @@ -177,7 +179,7 @@ REG_OP HBnkEnd2[] = { {NR,0x0,0x0,0x0} }; -/* Display 2 H SyncSt */ + REG_OP HSyncSt2[] = { {SR, BIT2+BIT1+BIT0, 0x38,0}, {CR, 0xFF, 0x27,3}, @@ -185,7 +187,7 @@ REG_OP HSyncSt2[] = { {NR,0x0,0x0,0x0} }; -/* Display 2 H SyncEnd */ + REG_OP HSyncEnd2[] = { {SR, BIT6+BIT5+BIT4, 0x38,0}, {CR, 0x1F, 0x28,3}, @@ -193,7 +195,7 @@ REG_OP HSyncEnd2[] = { {NR,0x0,0x0,0x0} }; -/* Display 2 V Total */ + REG_OP VTotal2[] = { {CR, 0xFF, 0x2B,0}, {CR, BIT0, 0x31,8}, @@ -202,7 +204,7 @@ REG_OP VTotal2[] = { {NR,0x0,0x0,0x0} }; -/* Display 2 V DispEnd */ + REG_OP VDispEnd2[] = { {CR, 0xFF, 0x2C,0}, {CR, BIT1, 0x31,8}, @@ -211,7 +213,7 @@ REG_OP VDispEnd2[] = { {NR,0x0,0x0,0x0} }; -/* Display 2 V BnkSt */ + REG_OP VBnkSt2[] = { {CR, 0xFF, 0x2D,0}, {CR, BIT3, 0x31,8}, @@ -220,14 +222,14 @@ REG_OP VBnkSt2[] = { {NR,0x0,0x0,0x0} }; -/* Display 2 V VBnkEnd2 */ + REG_OP VBnkEnd2[] = { {CR, 0xFF, 0x2E,0}, {CR, BIT4, 0x32,8}, {NR,0x0,0x0,0x0} }; -/* Display 2 V SyncSt */ + REG_OP VSyncSt2[] = { {CR, 0xFF, 0x2F,0}, {CR, BIT2, 0x31,8}, @@ -236,21 +238,21 @@ REG_OP VSyncSt2[] = { {NR,0x0,0x0,0x0} }; -/* Display 2 V SyncEnd */ + REG_OP VSyncEnd2[] = { {CR, BIT3+BIT2+BIT1+BIT0, 0x30,0}, {CR, BIT6+BIT5, 0x32,4}, {NR,0x0,0x0,0x0} }; -/* Display 2 Pitch */ + REG_OP Pitch2[] = { {CR, 0xFF, 0x3A,0}, {CR, 0x3F, 0x3B,8}, {NR,0x0,0x0,0x0} }; -/*============================================================================= */ + REG_OP HSource1[] = { {SR, 0xFF, 0x4B, 0}, {SR, BIT3+BIT2+BIT1+BIT0, 0x4C, 8}, |