[Hexagon] Add PIC support

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@256025 91177308-0d34-0410-b5e6-96231b3b80d8

5 files changed, 113 insertions, 0 deletions

diff --git a/test/CodeGen/Hexagon/pic-jumptables.ll b/test/CodeGen/Hexagon/pic-jumptables.ll
new file mode 100644
index 00000000000..271105cb4b5
--- /dev/null
+++ b/test/CodeGen/Hexagon/pic-jumptables.ll
@@ -0,0 +1,48 @@
+; RUN: llc -march=hexagon -relocation-model=pic < %s | FileCheck %s
+
+; CHECK: r{{[0-9]+}}{{ *}}={{ *}}add({{pc|PC}}{{ *}},{{ *}}##
+; CHECK: r{{[0-9]+}}{{ *}}={{ *}}memw(r{{[0-9]+}}{{ *}}+{{ *}}r{{[0-9]+}}{{ *}}<<{{ *}}#2)
+; CHECK: r{{[0-9]+}}{{ *}}={{ *}}add(r{{[0-9]+}}{{ *}},{{ *}}r{{[0-9]+}})
+
+
+define i32 @test(i32 %y) nounwind {
+entry:
+  switch i32 %y, label %sw.epilog [
+    i32 1, label %sw.bb
+    i32 2, label %sw.bb1
+    i32 3, label %sw.bb2
+    i32 4, label %sw.bb3
+    i32 5, label %sw.bb4
+  ]
+
+sw.bb:                                            ; preds = %entry
+  tail call void bitcast (void (...)* @baz1 to void ()*)() nounwind
+  br label %sw.epilog
+
+sw.bb1:                                           ; preds = %entry
+  tail call void @baz2(i32 2, i32 78) nounwind
+  br label %sw.epilog
+
+sw.bb2:                                           ; preds = %entry
+  tail call void @baz3(i32 59) nounwind
+  br label %sw.epilog
+
+sw.bb3:                                           ; preds = %entry
+  tail call void @baz4(i32 4, i32 14) nounwind
+  br label %sw.epilog
+
+sw.bb4:                                           ; preds = %entry
+  br label %sw.epilog
+
+sw.epilog:                                        ; preds = %sw.bb4, %sw.bb3, %sw.bb2, %sw.bb1, %sw.bb, %entry
+  %y.addr.0 = phi i32 [ %y, %entry ], [ 14, %sw.bb4 ], [ 4, %sw.bb3 ], [ 3, %sw.bb2 ], [ 2, %sw.bb1 ], [ 1, %sw.bb ]
+  ret i32 %y.addr.0
+}
+
+declare void @baz1(...)
+
+declare void @baz2(i32, i32)
+
+declare void @baz3(i32)
+
+declare void @baz4(i32, i32)
diff --git a/test/CodeGen/Hexagon/pic-simple.ll b/test/CodeGen/Hexagon/pic-simple.ll
new file mode 100644
index 00000000000..fa223d5372e
--- /dev/null
+++ b/test/CodeGen/Hexagon/pic-simple.ll
@@ -0,0 +1,22 @@
+; RUN: llc -march=hexagon -mcpu=hexagonv5 -relocation-model=pic < %s | FileCheck %s
+
+; CHECK: r{{[0-9]+}} = add({{pc|PC}}, ##_GLOBAL_OFFSET_TABLE_@PCREL)
+; CHECK: r{{[0-9]+}} = memw(r{{[0-9]+}}{{.*}}+{{.*}}##src@GOT)
+; CHECK: r{{[0-9]+}} = memw(r{{[0-9]+}}{{.*}}+{{.*}}##dst@GOT)
+
+@dst = external global i32
+@src = external global i32
+
+define i32 @foo() nounwind {
+entry:
+  %0 = load i32, i32* @src, align 4, !tbaa !0
+  store i32 %0, i32* @dst, align 4, !tbaa !0
+  %call = tail call i32 @baz(i32 %0) nounwind
+  ret i32 0
+}
+
+declare i32 @baz(i32)
+
+!0 = !{!"int", !1}
+!1 = !{!"omnipotent char", !2}
+!2 = !{!"Simple C/C++ TBAA"}
diff --git a/test/CodeGen/Hexagon/pic-static.ll b/test/CodeGen/Hexagon/pic-static.ll
new file mode 100644
index 00000000000..f4ccc6b9ee7
--- /dev/null
+++ b/test/CodeGen/Hexagon/pic-static.ll
@@ -0,0 +1,21 @@
+; RUN: llc -march=hexagon -mcpu=hexagonv5 -relocation-model=pic < %s | FileCheck %s
+
+; CHECK-DAG: r{{[0-9]+}} = add({{pc|PC}}, ##_GLOBAL_OFFSET_TABLE_@PCREL)
+; CHECK-DAG: r{{[0-9]+}} = add({{pc|PC}}, ##x@PCREL)
+; CHECK: r{{[0-9]+}} = memw(r{{[0-9]+}}{{.*}}+{{.*}}##bar@GOT)
+
+@x = internal global i32 9, align 4
+@bar = external global i32*
+
+define i32 @foo(i32 %y) nounwind {
+entry:
+  store i32* @x, i32** @bar, align 4, !tbaa !0
+  %0 = load i32, i32* @x, align 4, !tbaa !3
+  %add = add nsw i32 %0, %y
+  ret i32 %add
+}
+
+!0 = !{!"any pointer", !1}
+!1 = !{!"omnipotent char", !2}
+!2 = !{!"Simple C/C++ TBAA"}
+!3 = !{!"int", !1}
diff --git a/test/MC/Hexagon/got.s b/test/MC/Hexagon/got.s
new file mode 100644
index 00000000000..85409ee4a90
--- /dev/null
+++ b/test/MC/Hexagon/got.s
@@ -0,0 +1,11 @@
+# RUN: llvm-mc -arch=hexagon -filetype=obj %s | llvm-objdump -r - | FileCheck %s
+#
+
+# make sure the fixups emitted match what is
+# expected.
+.Lgot:
+    r0 = memw (r1 + ##foo@GOT)
+
+# CHECK: R_HEX_GOT_32_6_X foo
+# CHECK: R_HEX_GOT_11_X foo
+
diff --git a/test/MC/Hexagon/pcrel.s b/test/MC/Hexagon/pcrel.s
new file mode 100644
index 00000000000..368fea5c2b3
--- /dev/null
+++ b/test/MC/Hexagon/pcrel.s
@@ -0,0 +1,11 @@
+# RUN: llvm-mc -arch=hexagon -filetype=obj %s | llvm-objdump -r - | FileCheck %s
+#
+
+# make sure the fixups emitted match what is
+# expected.
+.Lpc:
+    r0 = add (pc, ##foo@PCREL)
+
+# CHECK: R_HEX_B32_PCREL_X
+# CHECK: R_HEX_6_PCREL_X
+