diff options
| author | Hawking Zhang <Hawking.Zhang@amd.com> | 2016-08-04 14:26:51 +0800 |
|---|---|---|
| committer | Nicolai Hähnle <nicolai.haehnle@amd.com> | 2017-10-22 23:05:59 +0200 |
| commit | dcae70769fb6e7f907b2c5d26219465fb13fe689 (patch) | |
| tree | 44f9935a67fa26a5132e4a79362752e53832898b | |
| parent | e580be90e88eeed95faa5452e343f3ec509517e5 (diff) | |
drm/amdgpu: add freesync ioctl definesfreesync
Change-Id: Id5d607fee4ae119015ca685a508a2ee140a8e331
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Flora Cui <Flora.Cui@amd.com>
| -rw-r--r-- | include/drm/amdgpu_drm.h | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/include/drm/amdgpu_drm.h b/include/drm/amdgpu_drm.h index 919248fb..a90bdc18 100644 --- a/include/drm/amdgpu_drm.h +++ b/include/drm/amdgpu_drm.h @@ -55,6 +55,9 @@ extern "C" { #define DRM_AMDGPU_FENCE_TO_HANDLE 0x14 #define DRM_AMDGPU_SCHED 0x15 +/* hybrid specific ioctls */ +#define DRM_AMDGPU_FREESYNC 0x5d + #define DRM_IOCTL_AMDGPU_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create) #define DRM_IOCTL_AMDGPU_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap) #define DRM_IOCTL_AMDGPU_CTX DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CTX, union drm_amdgpu_ctx) @@ -72,6 +75,9 @@ extern "C" { #define DRM_IOCTL_AMDGPU_FENCE_TO_HANDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_FENCE_TO_HANDLE, union drm_amdgpu_fence_to_handle) #define DRM_IOCTL_AMDGPU_SCHED DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_SCHED, union drm_amdgpu_sched) +/* hybrid specific ioctls */ +#define DRM_IOCTL_AMDGPU_FREESYNC DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_FREESYNC, struct drm_amdgpu_freesync) + #define AMDGPU_GEM_DOMAIN_CPU 0x1 #define AMDGPU_GEM_DOMAIN_GTT 0x2 #define AMDGPU_GEM_DOMAIN_VRAM 0x4 @@ -923,6 +929,19 @@ struct drm_amdgpu_info_vce_clock_table { #define AMDGPU_FAMILY_AI 141 /* Vega10 */ #define AMDGPU_FAMILY_RV 142 /* Raven */ +/* + * Definition of free sync enter and exit signals + * We may have more options in the future + */ +#define AMDGPU_FREESYNC_FULLSCREEN_ENTER 1 +#define AMDGPU_FREESYNC_FULLSCREEN_EXIT 2 + +struct drm_amdgpu_freesync { + __u32 op; /* AMDGPU_FREESYNC_FULLSCREEN_ENTER or */ + /* AMDGPU_FREESYNC_FULLSCREEN_ENTER */ + __u32 spare[7]; +}; + #if defined(__cplusplus) } #endif |