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| author | Iago Toral Quiroga <itoral@igalia.com> | 2018-11-27 08:57:13 +0100 |
|---|---|---|
| committer | Iago Toral Quiroga <itoral@igalia.com> | 2018-11-28 08:28:27 +0100 |
| commit | e55cbf26ea5ff56a80a55b38e3964ee13a5cfeff (patch) | |
| tree | ccd852be6dfea2e61890bd6b075a8a80cab546dc | |
| parent | 6f737b9207b49c6775355ae11e043a94e60ae3cf (diff) | |
intel/compiler: fix register allocation in opt_peephole_sel
This wasn't handling 64-bit cases properly. Found by inspection.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
| -rw-r--r-- | src/intel/compiler/brw_fs_sel_peephole.cpp | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/src/intel/compiler/brw_fs_sel_peephole.cpp b/src/intel/compiler/brw_fs_sel_peephole.cpp index fd02792bebc..6395b409b7c 100644 --- a/src/intel/compiler/brw_fs_sel_peephole.cpp +++ b/src/intel/compiler/brw_fs_sel_peephole.cpp @@ -198,8 +198,7 @@ fs_visitor::opt_peephole_sel() */ fs_reg src0(then_mov[i]->src[0]); if (src0.file == IMM) { - src0 = vgrf(glsl_type::float_type); - src0.type = then_mov[i]->src[0].type; + src0 = ibld.vgrf(then_mov[i]->src[0].type); ibld.MOV(src0, then_mov[i]->src[0]); } |