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authorTimur Kristóf <timur.kristof@gmail.com>2020-04-27 12:22:03 +0200
committerMarge Bot <eric+marge@anholt.net>2020-04-29 11:51:04 +0000
commitefa4976709afbbbfd430235bb8b71e6abb66d8e7 (patch)
treef311d57454b5dc16a4999ce49bd78ff87df76c27
parent7aa61c84fe47f139b96b29d39b3298f30b96c89c (diff)
radv: Use new linking helper to set default driver locations.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com> Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4388>
-rw-r--r--src/amd/vulkan/radv_pipeline.c50
-rw-r--r--src/amd/vulkan/radv_shader.h8
2 files changed, 58 insertions, 0 deletions
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index 2e535a33e39..ae584328ab4 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -2254,6 +2254,54 @@ radv_link_shaders(struct radv_pipeline *pipeline, nir_shader **shaders)
}
}
+static void
+radv_set_linked_driver_locations(struct radv_pipeline *pipeline, nir_shader **shaders,
+ struct radv_shader_info infos[MESA_SHADER_STAGES])
+{
+ bool has_tess = shaders[MESA_SHADER_TESS_CTRL];
+ bool has_gs = shaders[MESA_SHADER_GEOMETRY];
+
+ if (!has_tess && !has_gs)
+ return;
+
+ unsigned vs_info_idx = MESA_SHADER_VERTEX;
+ unsigned tes_info_idx = MESA_SHADER_TESS_EVAL;
+
+ if (pipeline->device->physical_device->rad_info.chip_class >= GFX9) {
+ /* These are merged into the next stage */
+ vs_info_idx = has_tess ? MESA_SHADER_TESS_CTRL : MESA_SHADER_GEOMETRY;
+ tes_info_idx = has_gs ? MESA_SHADER_GEOMETRY : MESA_SHADER_TESS_EVAL;
+ }
+
+ if (has_tess) {
+ nir_linked_io_var_info vs2tcs =
+ nir_assign_linked_io_var_locations(shaders[MESA_SHADER_VERTEX], shaders[MESA_SHADER_TESS_CTRL]);
+ nir_linked_io_var_info tcs2tes =
+ nir_assign_linked_io_var_locations(shaders[MESA_SHADER_TESS_CTRL], shaders[MESA_SHADER_TESS_EVAL]);
+
+ infos[vs_info_idx].vs.num_linked_outputs = vs2tcs.num_linked_io_vars;
+ infos[MESA_SHADER_TESS_CTRL].tcs.num_linked_inputs = vs2tcs.num_linked_io_vars;
+ infos[MESA_SHADER_TESS_CTRL].tcs.num_linked_outputs = tcs2tes.num_linked_io_vars;
+ infos[MESA_SHADER_TESS_CTRL].tcs.num_linked_patch_outputs = tcs2tes.num_linked_patch_io_vars;
+ infos[tes_info_idx].tes.num_linked_inputs = tcs2tes.num_linked_io_vars;
+ infos[tes_info_idx].tes.num_linked_patch_inputs = tcs2tes.num_linked_patch_io_vars;
+
+ if (has_gs) {
+ nir_linked_io_var_info tes2gs =
+ nir_assign_linked_io_var_locations(shaders[MESA_SHADER_TESS_EVAL], shaders[MESA_SHADER_GEOMETRY]);
+
+ infos[tes_info_idx].tes.num_linked_outputs = tes2gs.num_linked_io_vars;
+ infos[MESA_SHADER_GEOMETRY].gs.num_linked_inputs = tes2gs.num_linked_io_vars;
+ }
+ } else if (has_gs) {
+ nir_linked_io_var_info vs2gs =
+ nir_assign_linked_io_var_locations(shaders[MESA_SHADER_VERTEX], shaders[MESA_SHADER_GEOMETRY]);
+
+ infos[vs_info_idx].vs.num_linked_outputs = vs2gs.num_linked_io_vars;
+ infos[MESA_SHADER_GEOMETRY].gs.num_linked_inputs = vs2gs.num_linked_io_vars;
+ }
+}
+
static uint32_t
radv_get_attrib_stride(const VkPipelineVertexInputStateCreateInfo *input_state,
uint32_t attrib_binding)
@@ -2864,6 +2912,8 @@ void radv_create_shaders(struct radv_pipeline *pipeline,
if (!(flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT))
radv_link_shaders(pipeline, nir);
+ radv_set_linked_driver_locations(pipeline, nir, infos);
+
for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
if (nir[i]) {
/* do this again since information such as outputs_read can be out-of-date */
diff --git a/src/amd/vulkan/radv_shader.h b/src/amd/vulkan/radv_shader.h
index 608900b5419..d7c8119cd24 100644
--- a/src/amd/vulkan/radv_shader.h
+++ b/src/amd/vulkan/radv_shader.h
@@ -259,6 +259,7 @@ struct radv_shader_info {
bool as_es;
bool as_ls;
bool export_prim_id;
+ uint8_t num_linked_outputs;
} vs;
struct {
uint8_t output_usage_mask[VARYING_SLOT_VAR31 + 1];
@@ -273,6 +274,7 @@ struct radv_shader_info {
unsigned output_prim;
unsigned invocations;
unsigned es_type; /* GFX9: VS or TES */
+ uint8_t num_linked_inputs;
} gs;
struct {
uint8_t output_usage_mask[VARYING_SLOT_VAR31 + 1];
@@ -284,6 +286,9 @@ struct radv_shader_info {
bool ccw;
bool point_mode;
bool export_prim_id;
+ uint8_t num_linked_inputs;
+ uint8_t num_linked_patch_inputs;
+ uint8_t num_linked_outputs;
} tes;
struct {
bool force_persample;
@@ -321,6 +326,9 @@ struct radv_shader_info {
unsigned tcs_vertices_out;
uint32_t num_patches;
uint32_t lds_size;
+ uint8_t num_linked_inputs;
+ uint8_t num_linked_outputs;
+ uint8_t num_linked_patch_outputs;
} tcs;
struct radv_streamout_info so;