mmio: use intel_iosf.c for DPIO reads and writes

This makes it a bit more like the kernel, so we can go poke at DPIO and
other IOSF regs a bit more easily.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>

5 files changed, 42 insertions, 134 deletions

diff --git a/lib/Makefile.sources b/lib/Makefile.sources
index fd08c1f5..50720578 100644
--- a/lib/Makefile.sources
+++ b/lib/Makefile.sources
@@ -35,7 +35,6 @@ libintel_tools_la_SOURCES = 	\
 	rendercopy_gen8.c	\
 	rendercopy.h		\
 	intel_reg_map.c		\
-	intel_dpio.c		\
 	intel_iosf.c		\
 	igt_kms.c \
 	igt_kms.h \
diff --git a/lib/intel_dpio.c b/lib/intel_dpio.c
deleted file mode 100644
index 7e22095e..00000000
--- a/lib/intel_dpio.c
+++ /dev/null
@@ -1,105 +0,0 @@
-/*
- * Copyright © 2008 Intel Corporation
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- *    Vijay Purushothaman <vijay.a.purushothaman@intel.com>
- *
- */
-#include <unistd.h>
-#include <stdlib.h>
-#include <stdio.h>
-#include <err.h>
-#include "intel_gpu_tools.h"
-
-static uint32_t intel_display_reg_read(uint32_t reg)
-{
-	struct pci_device *dev = intel_get_pci_device();
-
-	if (IS_VALLEYVIEW(dev->device_id))
-		reg += VLV_DISPLAY_BASE;
-	return (*(volatile uint32_t*)((volatile char*)mmio + reg));
-}
-
-static void intel_display_reg_write(uint32_t reg, uint32_t val)
-{
-	volatile uint32_t *ptr;
-	struct pci_device *dev = intel_get_pci_device();
-
-	if (IS_VALLEYVIEW(dev->device_id))
-		reg += VLV_DISPLAY_BASE;
-	ptr = (volatile uint32_t*)((volatile char*)mmio + reg);
-	*ptr = val;
-}
-
-static int get_dpio_port(int phy) {
-
-	struct pci_device *dev = intel_get_pci_device();
-	int dpio_port;
-
-	if (IS_VALLEYVIEW(dev->device_id))
-		dpio_port = DPIO_PORTID;
-
-	return dpio_port;
-}
-
-/*
- * In SoCs like Valleyview some of the PLL & Lane control registers
- * can be accessed only through IO side band fabric called DPIO
- */
-uint32_t
-intel_dpio_reg_read(uint32_t reg, int phy)
-{
-	/* Check whether the side band fabric is ready to accept commands */
-	do {
-		usleep(1);
-	} while (intel_display_reg_read(DPIO_PKT) & DPIO_BUSY);
-
-	intel_display_reg_write(DPIO_REG, reg);
-	intel_display_reg_write(DPIO_PKT, DPIO_RID |
-				DPIO_OP_READ | get_dpio_port(phy) | DPIO_BYTE);
-	do {
-		usleep(1);
-	} while (intel_display_reg_read(DPIO_PKT) & DPIO_BUSY);
-
-	return intel_display_reg_read(DPIO_DATA);
-}
-
-/*
- * In SoCs like Valleyview some of the PLL & Lane control registers
- * can be accessed only through IO side band fabric called DPIO
- */
-void
-intel_dpio_reg_write(uint32_t reg, uint32_t val, int phy)
-{
-	/* Check whether the side band fabric is ready to accept commands */
-	do {
-		usleep(1);
-	} while (intel_display_reg_read(DPIO_PKT) & DPIO_BUSY);
-
-	intel_display_reg_write(DPIO_DATA, val);
-	intel_display_reg_write(DPIO_REG, reg);
-	intel_display_reg_write(DPIO_PKT, DPIO_RID |
-				DPIO_OP_WRITE | get_dpio_port(phy) | DPIO_BYTE);
-	do {
-		usleep(1);
-	} while (intel_display_reg_read(DPIO_PKT) & DPIO_BUSY);
-}
diff --git a/lib/intel_iosf.c b/lib/intel_iosf.c
index 0ab14df0..25b05db5 100644
--- a/lib/intel_iosf.c
+++ b/lib/intel_iosf.c
@@ -7,12 +7,14 @@
 
 #define TIMEOUT_US 500000
 
-static int vlv_punit_rw(uint32_t port, uint8_t opcode, uint8_t addr,
-			uint32_t *val)
+static int vlv_sideband_rw(uint32_t port, uint8_t opcode, uint8_t addr,
+			   uint32_t *val)
 {
 	volatile uint32_t *ptr;
 	int timeout = 0;
 	uint32_t cmd, devfn, be, bar;
+	int is_read = (opcode == PUNIT_OPCODE_REG_READ ||
+		       opcode == DPIO_OPCODE_REG_READ);
 
 	bar = 0;
 	be = 0xf;
@@ -27,14 +29,13 @@ static int vlv_punit_rw(uint32_t port, uint8_t opcode, uint8_t addr,
 
 	if (*ptr & IOSF_SB_BUSY) {
 		fprintf(stderr, "warning: pcode (%s) mailbox access failed\n",
-			opcode == PUNIT_OPCODE_REG_READ ?
-			"read" : "write");
+			is_read ? "read" : "write");
 		return -EAGAIN;
 	}
 
 	ptr = (volatile uint32_t*)((volatile char*)mmio + VLV_IOSF_ADDR);
 	*ptr = addr;
-	if (opcode == PUNIT_OPCODE_REG_WRITE) {
+	if (!is_read) {
 		ptr = (volatile uint32_t*)((volatile char*)mmio +
 					   VLV_IOSF_DATA);
 		*ptr = *val;
@@ -54,7 +55,7 @@ static int vlv_punit_rw(uint32_t port, uint8_t opcode, uint8_t addr,
 		return -ETIMEDOUT;
 	}
 
-	if (opcode == PUNIT_OPCODE_REG_READ) {
+	if (is_read) {
 		ptr = (volatile uint32_t*)((volatile char*)mmio +
 					   VLV_IOSF_DATA);
 		*val = *ptr;
@@ -66,20 +67,33 @@ static int vlv_punit_rw(uint32_t port, uint8_t opcode, uint8_t addr,
 
 int intel_punit_read(uint8_t addr, uint32_t *val)
 {
-	return vlv_punit_rw(IOSF_PORT_PUNIT, PUNIT_OPCODE_REG_READ, addr, val);
+	return vlv_sideband_rw(IOSF_PORT_PUNIT, PUNIT_OPCODE_REG_READ, addr, val);
 }
 
 int intel_punit_write(uint8_t addr, uint32_t val)
 {
-	return vlv_punit_rw(IOSF_PORT_PUNIT, PUNIT_OPCODE_REG_WRITE, addr, &val);
+	return vlv_sideband_rw(IOSF_PORT_PUNIT, PUNIT_OPCODE_REG_WRITE, addr, &val);
 }
 
 int intel_nc_read(uint8_t addr, uint32_t *val)
 {
-	return vlv_punit_rw(IOSF_PORT_NC, PUNIT_OPCODE_REG_READ, addr, val);
+	return vlv_sideband_rw(IOSF_PORT_NC, PUNIT_OPCODE_REG_READ, addr, val);
 }
 
 int intel_nc_write(uint8_t addr, uint32_t val)
 {
-	return vlv_punit_rw(IOSF_PORT_NC, PUNIT_OPCODE_REG_WRITE, addr, &val);
+	return vlv_sideband_rw(IOSF_PORT_NC, PUNIT_OPCODE_REG_WRITE, addr, &val);
+}
+
+uint32_t intel_dpio_reg_read(uint32_t reg, int phy)
+{
+	uint32_t val;
+
+	vlv_sideband_rw(IOSF_PORT_DPIO, DPIO_OPCODE_REG_READ, reg, &val);
+	return val;
+}
+
+void intel_dpio_reg_write(uint32_t reg, uint32_t val, int phy)
+{
+	vlv_sideband_rw(IOSF_PORT_DPIO, DPIO_OPCODE_REG_WRITE, reg, &val);
 }
diff --git a/lib/intel_reg.h b/lib/intel_reg.h
index 39949d13..4b3a1028 100644
--- a/lib/intel_reg.h
+++ b/lib/intel_reg.h
@@ -3552,32 +3552,32 @@ typedef enum {
 #define  SFUSE_STRAP_DDID_DETECTED	(1<<0)
 
 /* Valleyview related items */
+#define VLV_DISPLAY_BASE       0x180000
 
-/* Valleyview DPIO registers */
-#define VLV_DISPLAY_BASE	0x180000
-#define DPIO_PKT			0x2100
-#define  DPIO_RID			(0 << 24)
-#define  DPIO_OP_WRITE		(1 << 16)
-#define  DPIO_OP_READ		(0 << 16)
-#define  DPIO_PORTID		(0x12 << 8)
-#define  DPIO_BYTE			(0xf << 4)
-#define  DPIO_BUSY			(1 << 0)
-#define DPIO_DATA			0x2104
-#define DPIO_REG			0x2108
-
-/* VLV IOSF access */
-#define VLV_IOSF_DOORBELL_REQ			0x182100
+/*
+ * IOSF sideband
+ */
+#define VLV_IOSF_DOORBELL_REQ			(VLV_DISPLAY_BASE + 0x2100)
 #define   IOSF_DEVFN_SHIFT			24
 #define   IOSF_OPCODE_SHIFT			16
 #define   IOSF_PORT_SHIFT			8
 #define   IOSF_BYTE_ENABLES_SHIFT		4
 #define   IOSF_BAR_SHIFT			1
 #define   IOSF_SB_BUSY				(1<<0)
+#define   IOSF_PORT_BUNIT			0x3
 #define   IOSF_PORT_PUNIT			0x4
 #define   IOSF_PORT_NC				0x11
-#define VLV_IOSF_DATA				0x182104
-#define VLV_IOSF_ADDR				0x182108
-
+#define   IOSF_PORT_DPIO			0x12
+#define   IOSF_PORT_GPIO_NC			0x13
+#define   IOSF_PORT_CCK				0x14
+#define   IOSF_PORT_CCU				0xA9
+#define   IOSF_PORT_GPS_CORE			0x48
+#define   IOSF_PORT_FLISDSI			0x1B
+#define VLV_IOSF_DATA				(VLV_DISPLAY_BASE + 0x2104)
+#define VLV_IOSF_ADDR				(VLV_DISPLAY_BASE + 0x2108)
+
+#define DPIO_OPCODE_REG_READ			0
+#define DPIO_OPCODE_REG_WRITE			1
 #define PUNIT_OPCODE_REG_READ			6
 #define PUNIT_OPCODE_REG_WRITE			7
 
diff --git a/tools/quick_dump/Makefile.am b/tools/quick_dump/Makefile.am
index 9eb5f37a..1814315e 100644
--- a/tools/quick_dump/Makefile.am
+++ b/tools/quick_dump/Makefile.am
@@ -12,7 +12,7 @@ I915ChipsetPython_la_SOURCES = chipset_wrap_python.c intel_chipset.c \
 			       $(top_srcdir)/lib/intel_pci.c  \
 			       $(top_srcdir)/lib/intel_reg_map.c  \
 			       $(top_srcdir)/lib/intel_mmio.c  \
-			       $(top_srcdir)/lib/intel_dpio.c
+			       $(top_srcdir)/lib/intel_iosf.c
 
 chipset_wrap_python.c chipset.py: chipset.i
 	$(AM_V_GEN)$(SWIG) $(AX_SWIG_PYTHON_OPT) -I/usr/include -I$(top_srcdir)/lib -o $@ $<