quick_dump: Fix the indentation

Fix the spaces to use [the python standard] 4 soft spaces for tabe.
While here, add the proper vim tag so we don't do it again.

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>

2 files changed, 70 insertions, 67 deletions

diff --git a/tools/quick_dump/quick_dump.py b/tools/quick_dump/quick_dump.py
index 77744d49..4059bca7 100755
--- a/tools/quick_dump/quick_dump.py
+++ b/tools/quick_dump/quick_dump.py
@@ -6,6 +6,8 @@
 # register types:
 #  '' - normal register
 #  'DPIO' - DPIO register
+#
+# vim: tabstop=8 expandtab shiftwidth=4 softtabstop=4
 
 import argparse
 import os
@@ -16,17 +18,17 @@ import chipset
 import reg_access as reg
 
 def parse_file(file):
-	print('{0:^10s} | {1:^28s} | {2:^10s}'. format('offset', file.name, 'value'))
-	print('-' * 54)
-	for line in file:
-		register = ast.literal_eval(line)
-		if register[2] == 'DPIO':
-			val = reg.dpio_read(register[1], 0)
-		else:
-			val = reg.read(register[1])
-		intreg = int(register[1], 16)
-		print('{0:#010x} | {1:<28} | {2:#010x}'.format(intreg, register[0], val))
-	print('')
+    print('{0:^10s} | {1:^28s} | {2:^10s}'. format('offset', file.name, 'value'))
+    print('-' * 54)
+    for line in file:
+        register = ast.literal_eval(line)
+        if register[2] == 'DPIO':
+            val = reg.dpio_read(register[1], 0)
+        else:
+            val = reg.read(register[1])
+        intreg = int(register[1], 16)
+        print('{0:#010x} | {1:<28} | {2:#010x}'.format(intreg, register[0], val))
+    print('')
 
 
 parser = argparse.ArgumentParser(description='Dumb register dumper.')
@@ -36,39 +38,39 @@ parser.add_argument('profile', nargs='?', type=argparse.FileType('r'), default=N
 args = parser.parse_args()
 
 if reg.init() == False:
-	print("Register initialization failed")
-	sys.exit()
+    print("Register initialization failed")
+    sys.exit()
 
 # Put us where the script is
 os.chdir(os.path.dirname(sys.argv[0]))
 
 #parse anything named base_ these are assumed to apply for all gens.
 if args.baseless == False:
-	for root, dirs, files in os.walk('.'):
-		for name in files:
-			if name.startswith(("base_")):
-				file = open(name.rstrip(), 'r')
-				parse_file(file)
+    for root, dirs, files in os.walk('.'):
+        for name in files:
+            if name.startswith(("base_")):
+                file = open(name.rstrip(), 'r')
+                parse_file(file)
 
 if args.autodetect:
-	pci_dev = chipset.intel_get_pci_device()
-	devid = chipset.pcidev_to_devid(pci_dev)
-	if chipset.is_sandybridge(devid):
-		args.profile = open('sandybridge', 'r')
-	elif chipset.is_ivybridge(devid):
-		args.profile = open('ivybridge', 'r')
-	elif chipset.is_valleyview(devid):
-		args.profile = open('valleyview', 'r')
-	elif chipset.is_haswell(devid):
-		args.profile = open('haswell', 'r')
-	elif chipset.is_broadwell(devid):
-		args.profile = open('broadwell', 'r')
-	else:
-		print("Autodetect of devid " + hex(devid) + " failed")
+    pci_dev = chipset.intel_get_pci_device()
+    devid = chipset.pcidev_to_devid(pci_dev)
+    if chipset.is_sandybridge(devid):
+        args.profile = open('sandybridge', 'r')
+    elif chipset.is_ivybridge(devid):
+        args.profile = open('ivybridge', 'r')
+    elif chipset.is_valleyview(devid):
+        args.profile = open('valleyview', 'r')
+    elif chipset.is_haswell(devid):
+        args.profile = open('haswell', 'r')
+    elif chipset.is_broadwell(devid):
+        args.profile = open('broadwell', 'r')
+    else:
+        print("Autodetect of devid " + hex(devid) + " failed")
 
 if args.profile == None:
-	sys.exit()
+    sys.exit()
 
 for extra in args.profile:
-	extra_file = open(extra.rstrip(), 'r')
-	parse_file(extra_file)
+    extra_file = open(extra.rstrip(), 'r')
+    parse_file(extra_file)
diff --git a/tools/quick_dump/reg_access.py b/tools/quick_dump/reg_access.py
index cf6e0a46..85f9b57b 100755
--- a/tools/quick_dump/reg_access.py
+++ b/tools/quick_dump/reg_access.py
@@ -1,59 +1,60 @@
 #!/usr/bin/env python3
+# vim: tabstop=8 expandtab shiftwidth=4 softtabstop=4
 import chipset
 
 def read(reg):
-	reg = int(reg, 16)
-	val = chipset.intel_register_read(reg)
-	return val
+    reg = int(reg, 16)
+    val = chipset.intel_register_read(reg)
+    return val
 
 def write(reg, val):
-	chipset.intel_register_write(reg, val)
+    chipset.intel_register_write(reg, val)
 
 def gen6_forcewake_get():
-	write(0xa18c, 0x1)
-	read("0xa180")
+    write(0xa18c, 0x1)
+    read("0xa180")
 
 def mt_forcewake_get():
-	write(0xa188, 0x10001)
-	read("0xa180")
+    write(0xa188, 0x10001)
+    read("0xa180")
 
 def vlv_forcewake_get():
-	write(0x1300b0, 0x10001)
-	read("0x1300b4")
+    write(0x1300b0, 0x10001)
+    read("0x1300b4")
 
 # don't be clever, just try all possibilities
 def get_wake():
-	gen6_forcewake_get()
-	mt_forcewake_get()
-	vlv_forcewake_get()
+    gen6_forcewake_get()
+    mt_forcewake_get()
+    vlv_forcewake_get()
 
 def dpio_read(reg, phy):
-	reg = int(reg, 16)
-	phy = int(phy)
+    reg = int(reg, 16)
+    phy = int(phy)
 
-	val = chipset.intel_dpio_reg_read(reg, phy)
-	return val
+    val = chipset.intel_dpio_reg_read(reg, phy)
+    return val
 
 
 def init():
-	pci_dev = chipset.intel_get_pci_device()
-	ret = chipset.intel_register_access_init(pci_dev, 0)
-	if ret != 0:
-		print("Register access init failed");
-		return False
+    pci_dev = chipset.intel_get_pci_device()
+    ret = chipset.intel_register_access_init(pci_dev, 0)
+    if ret != 0:
+        print("Register access init failed");
+        return False
 
-	if chipset.intel_register_access_needs_fakewake():
-		print("Forcing forcewake. Don't expect your system to work after this.")
-		get_wake()
+    if chipset.intel_register_access_needs_fakewake():
+        print("Forcing forcewake. Don't expect your system to work after this.")
+        get_wake()
 
-	return True
+    return True
 
 if __name__ == "__main__":
-	import sys
+    import sys
 
-	if init() == False:
-		sys.exit()
+    if init() == False:
+        sys.exit()
 
-	reg = sys.argv[1]
-	print(hex(read(reg)))
-	chipset.intel_register_access_fini()
+    reg = sys.argv[1]
+    print(hex(read(reg)))
+    chipset.intel_register_access_fini()