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~mattst88/mesa
add-f-d-d
arb_gpu_shader5
ballot
bug-109404
compact
dead/csel
dead/double-scheduler
dead/g45-transposed-read
dead/i965-sched-v3
dead/lround
dead/lround2
dead/lvn
dead/nir-vec4-rc
dead/pspom
dead/spf
dead/validate-old
dead/vec4-neg-mul-cse
dead/vec4-rc
dead/vector-logic
deferred/locking
deferred/no-peephole-sel
double-scheduler
experiment/brwinst-struct
experiment/cfg
experiment/demorgan-reverse
experiment/fsgenerator
experiment/glsl_ir_ssa
experiment/opt-1-minus-x-into-swiz
experiment/sample_lz
experiment/single-i965-gen
experiment/ssa
experiment/ssa-before-fixups
for-mark
for-rafael
fp64
jenkins
lvn
master
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sched
sched-eot
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tag/oct-18-2013
tag/oct-2-2014
tag/oct-2-2014-2
vec4-lower-int-mul
vf-component-packing
wip/arb_shader_group_vote
wip/bool
wip/const-vf
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wip/dot
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wip/lround
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wip/sample_lz
wip/sched-eot
wip/unorm
wip/validate
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wip/vec4-lower-int-mul
mattst88's mesa repository
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2019-04-18
intel/compiler: Improve fix_3src_operand()
for-rafael
Matt Turner
1
-5
/
+18
2019-04-18
intel/compiler: Add unit tests for sat prop for different exec sizes
Matt Turner
1
-0
/
+68
2019-04-18
intel/compiler: Use SIMD16 instructions in fs saturate prop unit test
Matt Turner
1
-2
/
+2
2019-04-18
intel/fs: Remove fs_generator::generate_linterp from gen11+.
Rafael Antognolli
1
-43
/
+5
2019-04-18
intel/fs: Add a lowering pass for linear interpolation.
Rafael Antognolli
2
-0
/
+48
2019-04-18
intel/fs: Only convert to scalar on fs_generator.
Rafael Antognolli
4
-5
/
+5
2019-04-18
intel/fs: Only propagate saturation if exec_size is the same.
Rafael Antognolli
1
-1
/
+2
2019-04-18
anv/device: expose VK_KHR_shader_float16_int8 in gen8+
Iago Toral Quiroga
2
-0
/
+10
2019-04-18
anv/pipeline: support Float16 and Int8 SPIR-V capabilities in gen8+
Iago Toral Quiroga
1
-0
/
+2
2019-04-18
compiler/spirv: move the check for Int8 capability
Iago Toral Quiroga
1
-4
/
+3
2019-04-18
intel/compiler: validate region restrictions for mixed float mode
Iago Toral Quiroga
2
-0
/
+880
2019-04-18
intel/compiler: validate conversions between 64-bit and 8-bit types
Iago Toral Quiroga
2
-0
/
+105
2019-04-18
intel/compiler: validate region restrictions for half-float conversions
Iago Toral Quiroga
2
-1
/
+270
2019-04-18
intel/compiler: also set F execution type for mixed float mode in BDW
Iago Toral Quiroga
1
-16
/
+20
2019-04-18
intel/compiler: implement SIMD16 restrictions for mixed-float instructions
Iago Toral Quiroga
1
-0
/
+72
2019-04-18
intel/compiler: skip MAD algebraic optimization for half-float or mixed mode
Iago Toral Quiroga
1
-0
/
+4
2019-04-18
intel/compiler: remove inexact algebraic optimizations from the backend
Iago Toral Quiroga
1
-38
/
+1
2019-04-18
intel/compiler: fix cmod propagation for non 32-bit types
Iago Toral Quiroga
1
-4
/
+9
2019-04-18
intel/compiler: add a brw_reg_type_is_integer helper
Iago Toral Quiroga
1
-0
/
+18
2019-04-18
intel/compiler: implement is_zero, is_one, is_negative_one for 8-bit/16-bit
Iago Toral Quiroga
1
-0
/
+26
2019-04-18
intel/compiler: generalize the combine constants pass
Iago Toral Quiroga
1
-22
/
+212
2019-04-18
intel/eu: force stride of 2 on NULL register for Byte instructions
Iago Toral Quiroga
1
-0
/
+11
2019-04-18
intel/compiler: ask for an integer type if requesting an 8-bit type
Iago Toral Quiroga
1
-2
/
+3
2019-04-18
intel/compiler: rework conversion opcodes
Iago Toral Quiroga
1
-19
/
+22
2019-04-18
intel/compiler: activate 16-bit bit-size lowerings also for 8-bit
Iago Toral Quiroga
1
-1
/
+1
2019-04-18
intel/compiler: split is_partial_write() into two variants
Iago Toral Quiroga
11
-30
/
+54
2019-04-18
intel/compiler: workaround for SIMD8 half-float MAD in gen8
Iago Toral Quiroga
1
-11
/
+28
2019-04-18
intel/compiler: fix ddy for half-float in Broadwell
Iago Toral Quiroga
1
-2
/
+15
2019-04-18
intel/compiler: fix ddx and ddy for 16-bit float
Iago Toral Quiroga
1
-19
/
+18
2019-04-18
intel/compiler: set correct precision fields for 3-source float instructions
Iago Toral Quiroga
1
-0
/
+16
2019-04-18
intel/compiler: allow half-float on 3-source instructions since gen8
Iago Toral Quiroga
1
-1
/
+2
2019-04-18
intel/compiler: don't compact 3-src instructions with Src1Type or Src2Type bits
Iago Toral Quiroga
1
-1
/
+4
2019-04-18
intel/compiler: add new half-float register type for 3-src instructions
Iago Toral Quiroga
1
-0
/
+4
2019-04-18
intel/compiler: add instruction setters for Src1Type and Src2Type.
Iago Toral Quiroga
1
-0
/
+2
2019-04-18
intel/compiler: drop unnecessary temporary from 32-bit fsign implementation
Iago Toral Quiroga
1
-3
/
+2
2019-04-18
intel/compiler: implement 16-bit fsign
Iago Toral Quiroga
1
-1
/
+16
2019-04-18
intel/compiler: handle extended math restrictions for half-float
Iago Toral Quiroga
3
-12
/
+34
2019-04-18
intel/compiler: lower some 16-bit float operations to 32-bit
Iago Toral Quiroga
1
-0
/
+5
2019-04-18
intel/compiler: assert restrictions on conversions to half-float
Iago Toral Quiroga
1
-2
/
+3
2019-04-18
intel/compiler: handle b2i/b2f with other integer conversion opcodes
Iago Toral Quiroga
1
-8
/
+8
2019-04-18
intel/compiler: split float to 64-bit opcodes from int to 64-bit
Iago Toral Quiroga
1
-0
/
+7
2019-04-18
intel/compiler: add a NIR pass to lower conversions
Iago Toral Quiroga
5
-0
/
+175
2019-04-17
Add no_aos_sampling GALLIVM_PERF option
Dominik Drees
3
-4
/
+11
2019-04-17
ac: use struct/raw store intrinsics for 8-bit/16-bit int with LLVM 9+
Samuel Pitoiset
1
-14
/
+34
2019-04-17
ac: use struct/raw load intrinsics for 8-bit/16-bit int with LLVM 9+
Samuel Pitoiset
1
-12
/
+38
2019-04-17
ac: add support for more types with struct/raw LLVM intrinsics
Samuel Pitoiset
1
-20
/
+26
2019-04-17
radv: add VK_KHR_shader_atomic_int64 but disable it for now
Samuel Pitoiset
3
-0
/
+12
2019-04-17
ac/nir: add 64-bit SSBO atomic operations support
Samuel Pitoiset
1
-3
/
+7
2019-04-17
ac/nir: use new LLVM 8 intrinsics for SSBO atomics except cmpswap
Samuel Pitoiset
1
-13
/
+18
2019-04-17
gallivm: fix saturated signed add / sub with llvm 9
Roland Scheidegger
1
-0
/
+14
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