diff options
| author | Iago Toral Quiroga <itoral@igalia.com> | 2018-05-21 14:34:01 +0200 |
|---|---|---|
| committer | Juan A. Suarez Romero <jasuarez@igalia.com> | 2019-04-18 11:05:18 +0200 |
| commit | 4ab2b97a8fbc8fb07534ec92c9c5326889af290f (patch) | |
| tree | 97e630e99472b6702e99ac0d3ee27102edbcd49f | |
| parent | a8d8b1a1391b207d4b19b1ba864612837f1fd543 (diff) | |
intel/compiler: add instruction setters for Src1Type and Src2Type.
The original SrcType is a 3-bit field that takes a subset of the types
supported for the hardware for 3-source instructions. Since gen8,
when the half-float type was added, 3-source floating point operations
can use use mixed precision mode, where not all the operands have the
same floating-point precision. While the precision for the first operand
is taken from the type in SrcType, the bits in Src1Type (bit 36) and
Src2Type (bit 35) define the precision for the other operands
(0: normal precision, 1: half precision).
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
| -rw-r--r-- | src/intel/compiler/brw_inst.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/intel/compiler/brw_inst.h b/src/intel/compiler/brw_inst.h index 71316f12215..1f55d45125d 100644 --- a/src/intel/compiler/brw_inst.h +++ b/src/intel/compiler/brw_inst.h @@ -222,6 +222,8 @@ F8(3src_src1_negate, 39, 39, 40, 40) F8(3src_src1_abs, 38, 38, 39, 39) F8(3src_src0_negate, 37, 37, 38, 38) F8(3src_src0_abs, 36, 36, 37, 37) +F8(3src_a16_src1_type, -1, -1, 36, 36) +F8(3src_a16_src2_type, -1, -1, 35, 35) F8(3src_a16_flag_reg_nr, 34, 34, 33, 33) F8(3src_a16_flag_subreg_nr, 33, 33, 32, 32) FF(3src_a16_dst_reg_file, |