[PATCH] Update comment explaining the old buggy method for circumventing framebuffer

caching for CPU reads. Also, factor out to an inline function the code to
test register caching.

1 files changed, 64 insertions, 136 deletions

diff --git a/src/atimach64accel.c b/src/atimach64accel.c
index 8a21d4d..150fe4a 100644
--- a/src/atimach64accel.c
+++ b/src/atimach64accel.c
@@ -130,6 +130,54 @@ ATIMach64ValidateClip
     }
 }
 
+static __inline__ void TestRegisterCachingDP
+(
+    ScrnInfoPtr pScreenInfo
+)
+{
+    ATIPtr pATI = ATIPTR(pScreenInfo);
+
+    /*
+     * For debugging purposes, attempt to verify that each cached register
+     * should actually be cached.
+     */
+    TestRegisterCaching(SRC_CNTL);
+
+    TestRegisterCaching(HOST_CNTL);
+
+    TestRegisterCaching(PAT_REG0);
+    TestRegisterCaching(PAT_REG1);
+    TestRegisterCaching(PAT_CNTL);
+
+    if (RegisterIsCached(SC_LEFT_RIGHT) &&  /* Special case */
+        (CacheSlot(SC_LEFT_RIGHT) !=
+         (SetWord(inm(SC_RIGHT), 1) | SetWord(inm(SC_LEFT), 0))))
+    {
+        UncacheRegister(SC_LEFT_RIGHT);
+        xf86DrvMsg(pScreenInfo->scrnIndex, X_WARNING,
+            "SC_LEFT_RIGHT write cache disabled!\n");
+    }
+
+    if (RegisterIsCached(SC_TOP_BOTTOM) &&  /* Special case */
+        (CacheSlot(SC_TOP_BOTTOM) !=
+         (SetWord(inm(SC_BOTTOM), 1) | SetWord(inm(SC_TOP), 0))))
+    {
+        UncacheRegister(SC_TOP_BOTTOM);
+        xf86DrvMsg(pScreenInfo->scrnIndex, X_WARNING,
+            "SC_TOP_BOTTOM write cache disabled!\n");
+    }
+
+    TestRegisterCaching(DP_BKGD_CLR);
+    TestRegisterCaching(DP_FRGD_CLR);
+    TestRegisterCaching(DP_WRITE_MASK);
+    TestRegisterCaching(DP_PIX_WIDTH);
+    TestRegisterCaching(DP_MIX);
+
+    TestRegisterCaching(CLR_CMP_CLR);
+    TestRegisterCaching(CLR_CMP_MSK);
+    TestRegisterCaching(CLR_CMP_CNTL);
+}
+
 static __inline__ void TestRegisterCachingXV
 (
     ScrnInfoPtr pScreenInfo
@@ -283,7 +331,7 @@ ATIMach64Sync
             TestRegisterCaching(CLR_CMP_MSK);
 
             TestRegisterCachingXV(pScreenInfo);
-         }
+	}
 	pATI->NeedDRISync = FALSE;
 
     }
@@ -295,46 +343,7 @@ ATIMach64Sync
       
       if (pATI->OptionMMIOCache && pATI->OptionTestMMIOCache)
       {
-        /*
-         * For debugging purposes, attempt to verify that each cached register
-         * should actually be cached.
-         */
-        TestRegisterCaching(SRC_CNTL);
-
-        TestRegisterCaching(HOST_CNTL);
-
-        TestRegisterCaching(PAT_REG0);
-        TestRegisterCaching(PAT_REG1);
-        TestRegisterCaching(PAT_CNTL);
-
-        if (RegisterIsCached(SC_LEFT_RIGHT) &&  /* Special case */
-            (CacheSlot(SC_LEFT_RIGHT) !=
-             (SetWord(inm(SC_RIGHT), 1) | SetWord(inm(SC_LEFT), 0))))
-        {
-            UncacheRegister(SC_LEFT_RIGHT);
-            xf86DrvMsg(pScreenInfo->scrnIndex, X_WARNING,
-                "SC_LEFT_RIGHT write cache disabled!\n");
-        }
-
-        if (RegisterIsCached(SC_TOP_BOTTOM) &&  /* Special case */
-            (CacheSlot(SC_TOP_BOTTOM) !=
-             (SetWord(inm(SC_BOTTOM), 1) | SetWord(inm(SC_TOP), 0))))
-        {
-            UncacheRegister(SC_TOP_BOTTOM);
-            xf86DrvMsg(pScreenInfo->scrnIndex, X_WARNING,
-                "SC_TOP_BOTTOM write cache disabled!\n");
-        }
-
-        TestRegisterCaching(DP_BKGD_CLR);
-        TestRegisterCaching(DP_FRGD_CLR);
-        TestRegisterCaching(DP_WRITE_MASK);
-        TestRegisterCaching(DP_PIX_WIDTH);
-        TestRegisterCaching(DP_MIX);
-
-        TestRegisterCaching(CLR_CMP_CLR);
-        TestRegisterCaching(CLR_CMP_MSK);
-        TestRegisterCaching(CLR_CMP_CNTL);
-
+        TestRegisterCachingDP(pScreenInfo);
         TestRegisterCachingXV(pScreenInfo);
       }
     }
@@ -352,111 +361,30 @@ ATIMach64Sync
      * zeroes, so do it here.  This appears to be due to some kind of engine
      * caching of framebuffer data I haven't found any way of disabling, or
      * otherwise circumventing.  Thanks to Mark Vojkovich for the suggestion.
+     *
+     * pATI = *(volatile ATIPtr *)pATI->pMemory;
+     *
+     * Update:
+     * The above trick is buggy and is now replaced by actually invalidating
+     * the cache with the code below. The comment is left here for reference,
+     * DRI uses this trick and needs updating.
      */
+
      if (pATI->Chip >= ATI_CHIP_264VTB)
-      {
-          /*
+     {
+         /*
           * Flush the read-back cache (by turning on INVALIDATE_RB_CACHE),
           * otherwise the host might get stale data when reading through the
           * aperture.
-           */
+          */
          outr(MEM_BUF_CNTL, pATI->NewHW.mem_buf_cntl);
      }
   
-     if (!pATI->OptionMMIOCache || !pATI->OptionTestMMIOCache)
-         return;
-  
-     /*
-      * For debugging purposes, attempt to verify that each cached register
-      * should actually be cached.
-      */
-     TestRegisterCaching(SRC_CNTL);
-  
-     TestRegisterCaching(HOST_CNTL);
-  
-     TestRegisterCaching(PAT_REG0);
-     TestRegisterCaching(PAT_REG1);
-     TestRegisterCaching(PAT_CNTL);
-  
-     if (RegisterIsCached(SC_LEFT_RIGHT) &&      /* Special case */
-         (CacheSlot(SC_LEFT_RIGHT) !=
-          (SetWord(inm(SC_RIGHT), 1) | SetWord(inm(SC_LEFT), 0))))
+     if (pATI->OptionMMIOCache && pATI->OptionTestMMIOCache)
      {
-         UncacheRegister(SC_LEFT_RIGHT);
-         xf86DrvMsg(pScreenInfo->scrnIndex, X_WARNING,
-             "SC_LEFT_RIGHT write cache disabled!\n");
+         TestRegisterCachingDP(pScreenInfo);
+         TestRegisterCachingXV(pScreenInfo);
      }
-  
-     if (RegisterIsCached(SC_TOP_BOTTOM) &&      /* Special case */
-         (CacheSlot(SC_TOP_BOTTOM) !=
-          (SetWord(inm(SC_BOTTOM), 1) | SetWord(inm(SC_TOP), 0))))
-     {
-         UncacheRegister(SC_TOP_BOTTOM);
-         xf86DrvMsg(pScreenInfo->scrnIndex, X_WARNING,
-             "SC_TOP_BOTTOM write cache disabled!\n");
-     }
-  
-     TestRegisterCaching(DP_BKGD_CLR);
-     TestRegisterCaching(DP_FRGD_CLR);
-     TestRegisterCaching(DP_WRITE_MASK);
-     TestRegisterCaching(DP_MIX);
-  
-     TestRegisterCaching(CLR_CMP_CLR);
-     TestRegisterCaching(CLR_CMP_MSK);
-     TestRegisterCaching(CLR_CMP_CNTL);
-  
-     if (!pATI->Block1Base)
-         return;
-  
-     TestRegisterCaching(OVERLAY_Y_X_START);
-     TestRegisterCaching(OVERLAY_Y_X_END);
-  
-     TestRegisterCaching(OVERLAY_GRAPHICS_KEY_CLR);
-     TestRegisterCaching(OVERLAY_GRAPHICS_KEY_MSK);
-  
-     TestRegisterCaching(OVERLAY_KEY_CNTL);
-  
-     TestRegisterCaching(OVERLAY_SCALE_INC);
-     TestRegisterCaching(OVERLAY_SCALE_CNTL);
- 
-     TestRegisterCaching(SCALER_HEIGHT_WIDTH);
- 
-     TestRegisterCaching(SCALER_TEST);
- 
-     TestRegisterCaching(VIDEO_FORMAT);
- 
-     if (pATI->Chip < ATI_CHIP_264VTB)
-     {
-         TestRegisterCaching(BUF0_OFFSET);
-         TestRegisterCaching(BUF0_PITCH);
-         TestRegisterCaching(BUF1_OFFSET);
-         TestRegisterCaching(BUF1_PITCH);
- 
-         return;
-      }
-  
-     TestRegisterCaching(SCALER_BUF0_OFFSET);
-     TestRegisterCaching(SCALER_BUF1_OFFSET);
-     TestRegisterCaching(SCALER_BUF_PITCH);
- 
-     TestRegisterCaching(OVERLAY_EXCLUSIVE_HORZ);
-     TestRegisterCaching(OVERLAY_EXCLUSIVE_VERT);
- 
-     if (pATI->Chip < ATI_CHIP_264GTPRO)
-         return;
- 
-     TestRegisterCaching(SCALER_COLOUR_CNTL);
- 
-     TestRegisterCaching(SCALER_H_COEFF0);
-     TestRegisterCaching(SCALER_H_COEFF1);
-     TestRegisterCaching(SCALER_H_COEFF2);
-     TestRegisterCaching(SCALER_H_COEFF3);
-     TestRegisterCaching(SCALER_H_COEFF4);
- 
-     TestRegisterCaching(SCALER_BUF0_OFFSET_U);
-     TestRegisterCaching(SCALER_BUF0_OFFSET_V);
-     TestRegisterCaching(SCALER_BUF1_OFFSET_U);
-     TestRegisterCaching(SCALER_BUF1_OFFSET_V);
 }
 
 #ifdef USE_XAA