diff options
| author | George Fufutos <fufutos610@hotmail.com> | 2006-05-05 23:10:58 +0300 |
|---|---|---|
| committer | Luc Verhaegen <libv@skynet.be> | 2006-05-07 20:20:57 +0200 |
| commit | 701c58f3de6cac99236e0da89bd7574bd13fc224 (patch) | |
| tree | c625235330f2520a1859b2df7caccf3660de04c9 | |
| parent | 186f1d85286b860f26b1b5fd96e9623e5b4ae36f (diff) | |
[PATCH] Fix corruption when scaling 1-pixel wide pixmaps [0/1] (bug 807, Ivor Hewitt
ivor@ivor.org, Marc Aurele La France).
The problem shows itself when scaling a 1 pixel wide pixmap onto the screen,
the first CPU read of the framebuffer will return stale data.
Add support for manipulating the MEM_BUF_CNTL register and invalidating the
read-back (or read buffer) cache.
| -rw-r--r-- | src/atimach64.c | 3 | ||||
| -rw-r--r-- | src/atiregs.h | 13 | ||||
| -rw-r--r-- | src/atistruct.h | 2 |
3 files changed, 17 insertions, 1 deletions
diff --git a/src/atimach64.c b/src/atimach64.c index 0c31744..bb1add5 100644 --- a/src/atimach64.c +++ b/src/atimach64.c @@ -166,6 +166,7 @@ ATIMach64PreInit if (pATI->Chip >= ATI_CHIP_264VTB) { + pATIHW->mem_buf_cntl = inr(MEM_BUF_CNTL) | INVALIDATE_RB_CACHE; pATIHW->mem_cntl = (pATI->LockData.mem_cntl & ~(CTL_MEM_LOWER_APER_ENDIAN | CTL_MEM_UPPER_APER_ENDIAN)) | SetBits(CTL_MEM_APER_BYTE_ENDIAN, CTL_MEM_LOWER_APER_ENDIAN); @@ -407,6 +408,7 @@ ATIMach64Save if (pATI->Chip >= ATI_CHIP_264VTB) { + pATIHW->mem_buf_cntl = inr(MEM_BUF_CNTL) | INVALIDATE_RB_CACHE; pATIHW->mem_cntl = inr(MEM_CNTL); pATIHW->mpp_config = inr(MPP_CONFIG); pATIHW->mpp_strobe_seq = inr(MPP_STROBE_SEQ); @@ -1024,6 +1026,7 @@ ATIMach64Set if (pATI->Chip >= ATI_CHIP_264VTB) { + outr(MEM_BUF_CNTL, pATIHW->mem_buf_cntl); outr(MEM_CNTL, pATIHW->mem_cntl); outr(MPP_CONFIG, pATIHW->mpp_config); outr(MPP_STROBE_SEQ, pATIHW->mpp_strobe_seq); diff --git a/src/atiregs.h b/src/atiregs.h index f9730c7..102347b 100644 --- a/src/atiregs.h +++ b/src/atiregs.h @@ -692,6 +692,19 @@ /* ? 0xf8000000ul */ #define TIMER_CONFIG BlockIOTag(0x0au) /* VTB/GTB/LT */ #define MEM_BUF_CNTL BlockIOTag(0x0bu) /* VTB/GTB/LT */ +#define Z_WB_FLUSH 0x00000007ul +#define Z_WB_FLUSH_P 0x0000000ful /* GTPro */ +#define VID_WB_FLUSH_P 0x000000f0ul /* GTPro */ +#define VID_WB_FLUSH_MSB 0x00000100ul +#define GUI_WB_FLUSH_P 0x00001f00ul /* GTPro */ +#define HST_WB_FLUSH_P 0x0000e000ul /* GTPro */ +#define SCL_MIN_BURST_LEN 0x001f0000ul +#define SCL_THRESH 0x003f0000ul /* GTPro */ +/* ? 0x00400000ul */ +#define INVALIDATE_RB_CACHE 0x00800000ul +#define HST_WB_FLUSH 0x03000000ul +#define VID_WB_FLUSH 0x1c000000ul +#define GUI_WB_FLUSH 0xe0000000ul #define SHARED_CNTL BlockIOTag(0x0cu) /* VTB/GTB/LT */ #define SHARED_MEM_CONFIG BlockIOTag(0x0du) /* VTB/GTB/LT */ #define MEM_ADDR_CONFIG BlockIOTag(0x0du) /* GTPro */ diff --git a/src/atistruct.h b/src/atistruct.h index 852df48..7ea0d8d 100644 --- a/src/atistruct.h +++ b/src/atistruct.h @@ -115,7 +115,7 @@ typedef struct _ATIHWRec /* Mach64 CPIO registers */ CARD32 crtc_h_total_disp, crtc_h_sync_strt_wid, crtc_v_total_disp, crtc_v_sync_strt_wid, - crtc_off_pitch, crtc_gen_cntl, dsp_config, dsp_on_off, + crtc_off_pitch, crtc_gen_cntl, dsp_config, dsp_on_off, mem_buf_cntl, ovr_clr, ovr_wid_left_right, ovr_wid_top_bottom, cur_clr0, cur_clr1, cur_offset, cur_horz_vert_posn, cur_horz_vert_off, |