[PATCH] Minor MMIO cache testing fixes.

Remove superflous MMIO cache test. Also, move the test for Block1Base outside
TestRegisterCachingXV() (for scaler and overlay registers) in preperation for
caching some 3D registers as well.

1 files changed, 70 insertions, 79 deletions

diff --git a/src/atimach64accel.c b/src/atimach64accel.c
index 150fe4a..bc4ff4c 100644
--- a/src/atimach64accel.c
+++ b/src/atimach64accel.c
@@ -130,17 +130,11 @@ ATIMach64ValidateClip
     }
 }
 
-static __inline__ void TestRegisterCachingDP
-(
-    ScrnInfoPtr pScreenInfo
-)
+static __inline__ void
+TestRegisterCachingDP(ScrnInfoPtr pScreenInfo)
 {
     ATIPtr pATI = ATIPTR(pScreenInfo);
 
-    /*
-     * For debugging purposes, attempt to verify that each cached register
-     * should actually be cached.
-     */
     TestRegisterCaching(SRC_CNTL);
 
     TestRegisterCaching(HOST_CNTL);
@@ -178,63 +172,58 @@ static __inline__ void TestRegisterCachingDP
     TestRegisterCaching(CLR_CMP_CNTL);
 }
 
-static __inline__ void TestRegisterCachingXV
-(
-    ScrnInfoPtr pScreenInfo
-)
+static __inline__ void
+TestRegisterCachingXV(ScrnInfoPtr pScreenInfo)
 {
     ATIPtr pATI = ATIPTR(pScreenInfo);
 
-    if (pATI->Block1Base)
-    {
-        TestRegisterCaching(OVERLAY_Y_X_START);
-        TestRegisterCaching(OVERLAY_Y_X_END);
+    TestRegisterCaching(OVERLAY_Y_X_START);
+    TestRegisterCaching(OVERLAY_Y_X_END);
 
-        TestRegisterCaching(OVERLAY_GRAPHICS_KEY_CLR);
-        TestRegisterCaching(OVERLAY_GRAPHICS_KEY_MSK);
+    TestRegisterCaching(OVERLAY_GRAPHICS_KEY_CLR);
+    TestRegisterCaching(OVERLAY_GRAPHICS_KEY_MSK);
 
-        TestRegisterCaching(OVERLAY_KEY_CNTL);
+    TestRegisterCaching(OVERLAY_KEY_CNTL);
 
-        TestRegisterCaching(OVERLAY_SCALE_INC);
-        TestRegisterCaching(OVERLAY_SCALE_CNTL);
+    TestRegisterCaching(OVERLAY_SCALE_INC);
+    TestRegisterCaching(OVERLAY_SCALE_CNTL);
 
-        TestRegisterCaching(SCALER_HEIGHT_WIDTH);
+    TestRegisterCaching(SCALER_HEIGHT_WIDTH);
 
-        TestRegisterCaching(SCALER_TEST);
+    TestRegisterCaching(SCALER_TEST);
 
-        TestRegisterCaching(VIDEO_FORMAT);
+    TestRegisterCaching(VIDEO_FORMAT);
 
-        if (pATI->Chip < ATI_CHIP_264VTB)
-        {
-            TestRegisterCaching(BUF0_OFFSET);
-            TestRegisterCaching(BUF0_PITCH);
-            TestRegisterCaching(BUF1_OFFSET);
-            TestRegisterCaching(BUF1_PITCH);
-        }
-        else
-        {
-            TestRegisterCaching(SCALER_BUF0_OFFSET);
-            TestRegisterCaching(SCALER_BUF1_OFFSET);
-            TestRegisterCaching(SCALER_BUF_PITCH);
+    if (pATI->Chip < ATI_CHIP_264VTB)
+    {
+        TestRegisterCaching(BUF0_OFFSET);
+        TestRegisterCaching(BUF0_PITCH);
+        TestRegisterCaching(BUF1_OFFSET);
+        TestRegisterCaching(BUF1_PITCH);
+    }
+    else
+    {
+        TestRegisterCaching(SCALER_BUF0_OFFSET);
+        TestRegisterCaching(SCALER_BUF1_OFFSET);
+        TestRegisterCaching(SCALER_BUF_PITCH);
 
-            TestRegisterCaching(OVERLAY_EXCLUSIVE_HORZ);
-            TestRegisterCaching(OVERLAY_EXCLUSIVE_VERT);
+        TestRegisterCaching(OVERLAY_EXCLUSIVE_HORZ);
+        TestRegisterCaching(OVERLAY_EXCLUSIVE_VERT);
 
-            if (pATI->Chip >= ATI_CHIP_264GTPRO)
-            {
-                TestRegisterCaching(SCALER_COLOUR_CNTL);
-
-                TestRegisterCaching(SCALER_H_COEFF0);
-                TestRegisterCaching(SCALER_H_COEFF1);
-                TestRegisterCaching(SCALER_H_COEFF2);
-                TestRegisterCaching(SCALER_H_COEFF3);
-                TestRegisterCaching(SCALER_H_COEFF4);
-
-                TestRegisterCaching(SCALER_BUF0_OFFSET_U);
-                TestRegisterCaching(SCALER_BUF0_OFFSET_V);
-                TestRegisterCaching(SCALER_BUF1_OFFSET_U);
-                TestRegisterCaching(SCALER_BUF1_OFFSET_V);
-            }
+        if (pATI->Chip >= ATI_CHIP_264GTPRO)
+        {
+            TestRegisterCaching(SCALER_COLOUR_CNTL);
+
+            TestRegisterCaching(SCALER_H_COEFF0);
+            TestRegisterCaching(SCALER_H_COEFF1);
+            TestRegisterCaching(SCALER_H_COEFF2);
+            TestRegisterCaching(SCALER_H_COEFF3);
+            TestRegisterCaching(SCALER_H_COEFF4);
+
+            TestRegisterCaching(SCALER_BUF0_OFFSET_U);
+            TestRegisterCaching(SCALER_BUF0_OFFSET_V);
+            TestRegisterCaching(SCALER_BUF1_OFFSET_U);
+            TestRegisterCaching(SCALER_BUF1_OFFSET_V);
         }
     }
 }
@@ -325,12 +314,13 @@ ATIMach64Sync
 	  
 	    /* Only check registers we didn't restore */
 	    TestRegisterCaching(PAT_REG0);
-            TestRegisterCaching(PAT_REG1);
+	    TestRegisterCaching(PAT_REG1);
 
-            TestRegisterCaching(CLR_CMP_CLR);
-            TestRegisterCaching(CLR_CMP_MSK);
+	    TestRegisterCaching(CLR_CMP_CLR);
+	    TestRegisterCaching(CLR_CMP_MSK);
 
-            TestRegisterCachingXV(pScreenInfo);
+	    if (pATI->Block1Base)
+	        TestRegisterCachingXV(pScreenInfo);
 	}
 	pATI->NeedDRISync = FALSE;
 
@@ -343,48 +333,49 @@ ATIMach64Sync
       
       if (pATI->OptionMMIOCache && pATI->OptionTestMMIOCache)
       {
+        /*
+         * For debugging purposes, attempt to verify that each cached register
+         * should actually be cached.
+         */
         TestRegisterCachingDP(pScreenInfo);
-        TestRegisterCachingXV(pScreenInfo);
+
+        if (pATI->Block1Base)
+            TestRegisterCachingXV(pScreenInfo);
       }
     }
 
 #ifdef USE_EXA
     /* EXA sets pEXA->needsSync to FALSE on its own */
 #endif
+
 #ifdef USE_XAA
     if (pATI->pXAAInfo)
       pATI->pXAAInfo->NeedToSync = FALSE;
 #endif
 
+    if (pATI->Chip >= ATI_CHIP_264VTB)
+    {
+        /*
+         * Flush the read-back cache (by turning on INVALIDATE_RB_CACHE),
+         * otherwise the host might get stale data when reading through the
+         * aperture.
+         */
+        outr(MEM_BUF_CNTL, pATI->NewHW.mem_buf_cntl);
+    }
+
     /*
+     * Note:
+     * Before actually invalidating the read-back cache, the mach64 driver
+     * was using the trick below which is buggy. The code is left here for
+     * reference, DRI uses this trick and needs updating.
+     *
      * For VTB's and later, the first CPU read of the framebuffer will return
      * zeroes, so do it here.  This appears to be due to some kind of engine
      * caching of framebuffer data I haven't found any way of disabling, or
      * otherwise circumventing.  Thanks to Mark Vojkovich for the suggestion.
      *
      * pATI = *(volatile ATIPtr *)pATI->pMemory;
-     *
-     * Update:
-     * The above trick is buggy and is now replaced by actually invalidating
-     * the cache with the code below. The comment is left here for reference,
-     * DRI uses this trick and needs updating.
      */
-
-     if (pATI->Chip >= ATI_CHIP_264VTB)
-     {
-         /*
-          * Flush the read-back cache (by turning on INVALIDATE_RB_CACHE),
-          * otherwise the host might get stale data when reading through the
-          * aperture.
-          */
-         outr(MEM_BUF_CNTL, pATI->NewHW.mem_buf_cntl);
-     }
-  
-     if (pATI->OptionMMIOCache && pATI->OptionTestMMIOCache)
-     {
-         TestRegisterCachingDP(pScreenInfo);
-         TestRegisterCachingXV(pScreenInfo);
-     }
 }
 
 #ifdef USE_XAA