diff options
| author | Marek Olšák <marek.olsak@amd.com> | 2018-05-02 19:54:35 -0400 |
|---|---|---|
| committer | Marek Olšák <marek.olsak@amd.com> | 2018-05-10 18:40:10 -0400 |
| commit | 9b1fdfc541ed0eb62632e893b2142500bb003453 (patch) | |
| tree | b6ebd09c3b782f8153d29fe312e585409feb35e2 | |
| parent | d26696283d494822f2df72a6b94d51e70f91c4d9 (diff) | |
ac/gpu_info: add has_2d_tiling
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
| -rw-r--r-- | src/amd/common/ac_gpu_info.c | 2 | ||||
| -rw-r--r-- | src/amd/common/ac_gpu_info.h | 1 | ||||
| -rw-r--r-- | src/gallium/drivers/radeonsi/si_get.c | 6 | ||||
| -rw-r--r-- | src/gallium/winsys/radeon/drm/radeon_drm_winsys.c | 2 |
4 files changed, 6 insertions, 5 deletions
diff --git a/src/amd/common/ac_gpu_info.c b/src/amd/common/ac_gpu_info.c index 7e40ffcf3e..906e76ba05 100644 --- a/src/amd/common/ac_gpu_info.c +++ b/src/amd/common/ac_gpu_info.c @@ -337,6 +337,7 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle dev, info->has_sparse_vm_mappings = info->chip_class >= CIK && info->chip_class <= VI && info->drm_minor >= 13; + info->has_2d_tiling = true; info->num_render_backends = amdinfo->rb_pipes; /* The value returned by the kernel driver was wrong. */ @@ -496,6 +497,7 @@ void ac_print_gpu_info(struct radeon_info *info) printf(" has_indirect_compute_dispatch = %u\n", info->has_indirect_compute_dispatch); printf(" has_unaligned_shader_loads = %u\n", info->has_unaligned_shader_loads); printf(" has_sparse_vm_mappings = %u\n", info->has_sparse_vm_mappings); + printf(" has_2d_tiling = %u\n", info->has_2d_tiling); printf("Shader core info:\n"); printf(" max_shader_clock = %i\n", info->max_shader_clock); diff --git a/src/amd/common/ac_gpu_info.h b/src/amd/common/ac_gpu_info.h index 7caa654369..fb44f7c8af 100644 --- a/src/amd/common/ac_gpu_info.h +++ b/src/amd/common/ac_gpu_info.h @@ -108,6 +108,7 @@ struct radeon_info { bool has_indirect_compute_dispatch; bool has_unaligned_shader_loads; bool has_sparse_vm_mappings; + bool has_2d_tiling; /* Shader cores. */ uint32_t r600_max_quad_pipes; /* wave size / 16 */ diff --git a/src/gallium/drivers/radeonsi/si_get.c b/src/gallium/drivers/radeonsi/si_get.c index ef74cd457b..757192f309 100644 --- a/src/gallium/drivers/radeonsi/si_get.c +++ b/src/gallium/drivers/radeonsi/si_get.c @@ -198,11 +198,7 @@ static int si_get_param(struct pipe_screen *pscreen, enum pipe_cap param) sscreen->info.has_gpu_reset_counter_query; case PIPE_CAP_TEXTURE_MULTISAMPLE: - /* 2D tiling on CIK is supported since DRM 2.35.0 */ - return sscreen->info.chip_class < CIK || - (sscreen->info.drm_major == 2 && - sscreen->info.drm_minor >= 35) || - sscreen->info.drm_major == 3; + return sscreen->info.has_2d_tiling; case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT: return SI_MAP_BUFFER_ALIGNMENT; diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c index 3585b35af3..cb8c7ce9fc 100644 --- a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c +++ b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c @@ -548,6 +548,8 @@ static bool do_winsys_init(struct radeon_drm_winsys *ws) ws->info.has_unaligned_shader_loads = ws->info.chip_class == CIK && ws->info.drm_minor >= 50; ws->info.has_sparse_vm_mappings = false; + /* 2D tiling on CIK is supported since DRM 2.35.0 */ + ws->info.has_2d_tiling = ws->info.chip_class <= SI || ws->info.drm_minor >= 35; ws->check_vm = strstr(debug_get_option("R600_DEBUG", ""), "check_vm") != NULL; |