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| author | Marek Olšák <marek.olsak@amd.com> | 2018-05-01 20:16:19 -0400 |
|---|---|---|
| committer | Marek Olšák <marek.olsak@amd.com> | 2018-05-10 18:26:32 -0400 |
| commit | 597b9e881083533b987dbcbb8f679ca1eefff974 (patch) | |
| tree | f13e89dff4287a1b43560d52fe15445fac160fab | |
| parent | b784561c1a0c518f2e7bfe8fcb7b9b900d427bcb (diff) | |
radeonsi/gfx9: work around a GPU hang due to broken indirect indexing in LLVM
Fixes: 6d19120da85 "radeonsi/gfx9: workaround for INTERP with indirect indexing"
Cc: 18.1 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
| -rw-r--r-- | src/gallium/drivers/radeonsi/si_get.c | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/src/gallium/drivers/radeonsi/si_get.c b/src/gallium/drivers/radeonsi/si_get.c index d4e0eab187..c31ab43cb4 100644 --- a/src/gallium/drivers/radeonsi/si_get.c +++ b/src/gallium/drivers/radeonsi/si_get.c @@ -494,6 +494,15 @@ static int si_get_shader_param(struct pipe_screen* pscreen, !sscreen->llvm_has_working_vgpr_indexing) return 0; + /* Doing indirect indexing on GFX9 with LLVM 6.0 hangs. + * This means we don't support INTERP instructions with + * indirect indexing on inputs. + */ + if (shader == PIPE_SHADER_FRAGMENT && + !sscreen->llvm_has_working_vgpr_indexing && + HAVE_LLVM < 0x0700) + return 0; + /* TCS and TES load inputs directly from LDS or offchip * memory, so indirect indexing is always supported. * PS has to support indirect indexing, because we can't |