ac/gpu_info: add has_eqaa_surface_allocator

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

4 files changed, 7 insertions, 3 deletions

diff --git a/src/amd/common/ac_gpu_info.c b/src/amd/common/ac_gpu_info.c
index 7678a18b35..f05dd77a21 100644
--- a/src/amd/common/ac_gpu_info.c
+++ b/src/amd/common/ac_gpu_info.c
@@ -322,6 +322,7 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle dev,
 	info->has_bo_metadata = true;
 	info->has_gpu_reset_status_query = true;
 	info->has_gpu_reset_counter_query = false;
+	info->has_eqaa_surface_allocator = true;
 
 	info->num_render_backends = amdinfo->rb_pipes;
 	/* The value returned by the kernel driver was wrong. */
@@ -460,7 +461,7 @@ void ac_print_gpu_info(struct radeon_info *info)
 	printf("    vce_fw_version = %u\n", info->vce_fw_version);
 	printf("    vce_harvest_config = %i\n", info->vce_harvest_config);
 
-	printf("Kernel info:\n");
+	printf("Kernel & winsys capabilities:\n");
 	printf("    drm = %i.%i.%i\n", info->drm_major,
 	       info->drm_minor, info->drm_patchlevel);
 	printf("    has_userptr = %i\n", info->has_userptr);
@@ -475,6 +476,7 @@ void ac_print_gpu_info(struct radeon_info *info)
 	printf("    has_bo_metadata = %u\n", info->has_bo_metadata);
 	printf("    has_gpu_reset_status_query = %u\n", info->has_gpu_reset_status_query);
 	printf("    has_gpu_reset_counter_query = %u\n", info->has_gpu_reset_counter_query);
+	printf("    has_eqaa_surface_allocator = %u\n", info->has_eqaa_surface_allocator);
 
 	printf("Shader core info:\n");
 	printf("    max_shader_clock = %i\n", info->max_shader_clock);
diff --git a/src/amd/common/ac_gpu_info.h b/src/amd/common/ac_gpu_info.h
index f5b74579ef..f8e4adf0d4 100644
--- a/src/amd/common/ac_gpu_info.h
+++ b/src/amd/common/ac_gpu_info.h
@@ -86,7 +86,7 @@ struct radeon_info {
 	uint32_t                    vce_fw_version;
 	uint32_t                    vce_harvest_config;
 
-	/* Kernel info. */
+	/* Kernel & winsys capabilities. */
 	uint32_t                    drm_major; /* version */
 	uint32_t                    drm_minor;
 	uint32_t                    drm_patchlevel;
@@ -102,6 +102,7 @@ struct radeon_info {
 	bool                        has_bo_metadata;
 	bool                        has_gpu_reset_status_query;
 	bool                        has_gpu_reset_counter_query;
+	bool                        has_eqaa_surface_allocator;
 
 	/* Shader cores. */
 	uint32_t                    r600_max_quad_pipes; /* wave size / 16 */
diff --git a/src/gallium/drivers/radeonsi/si_pipe.c b/src/gallium/drivers/radeonsi/si_pipe.c
index bf61b0071e..fe0a20ba6c 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.c
+++ b/src/gallium/drivers/radeonsi/si_pipe.c
@@ -1082,7 +1082,7 @@ struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws,
 	 *
 	 * Only MSAA color and depth buffers are overriden.
 	 */
-	if (sscreen->info.drm_major == 3) {
+	if (sscreen->info.has_eqaa_surface_allocator) {
 		const char *eqaa = debug_get_option("EQAA", NULL);
 		unsigned s,z,f;
 
diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
index 7189b61ef1..1eecb23d9d 100644
--- a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
@@ -536,6 +536,7 @@ static bool do_winsys_init(struct radeon_drm_winsys *ws)
     ws->info.has_bo_metadata = false;
     ws->info.has_gpu_reset_status_query = false;
     ws->info.has_gpu_reset_counter_query = ws->info.drm_minor >= 43;
+    ws->info.has_eqaa_surface_allocator = false;
 
     ws->check_vm = strstr(debug_get_option("R600_DEBUG", ""), "check_vm") != NULL;