diff options
| author | Zhigang Gong <zhigang.gong@intel.com> | 2015-03-16 09:36:07 +0800 |
|---|---|---|
| committer | Zhigang Gong <zhigang.gong@intel.com> | 2015-03-16 10:16:06 +0800 |
| commit | a153aba8d861cfffe65309be670dba5d7fcb285f (patch) | |
| tree | dbc9a83a2dde4b43e703373b6e98e9f02006d953 | |
| parent | 1fc929737feeb14115bd63a9bb95b56adc6f94bd (diff) | |
GBE: fix an image related bugs.
The bug was introduces when we removed the hacky invalid
register. Now we will not pass in a fixed count of coordinates
for the typed_write instruction.
Signed-off-by: Zhigang Gong <zhigang.gong@intel.com>
Reviewed-by: "Yang, Rong R" <rong.r.yang@intel.com>
| -rw-r--r-- | backend/src/backend/gen_insn_selection.cpp | 13 | ||||
| -rw-r--r-- | backend/src/ir/instruction.cpp | 28 |
2 files changed, 24 insertions, 17 deletions
diff --git a/backend/src/backend/gen_insn_selection.cpp b/backend/src/backend/gen_insn_selection.cpp index 2b166b13..c2402618 100644 --- a/backend/src/backend/gen_insn_selection.cpp +++ b/backend/src/backend/gen_insn_selection.cpp @@ -4411,19 +4411,20 @@ namespace gbe msgs[i] = sel.selReg(sel.reg(FAMILY_DWORD), TYPE_U32); } else { uint32_t valueID = 0; - msgs[0] = sel.selReg(sel.reg(FAMILY_DWORD), TYPE_U32); - for(uint32_t msgID = 1; msgID < 1 + dim; msgID++, valueID++) + uint32_t msgID = 0; + msgs[msgID++] = sel.selReg(sel.reg(FAMILY_DWORD), TYPE_U32); + for(; msgID < 1 + dim; msgID++, valueID++) msgs[msgID] = sel.selReg(insn.getSrc(msgID - 1), insn.getCoordType()); // fake v. if (dim < 2) - msgs[2] = sel.selReg(sel.reg(FAMILY_DWORD), TYPE_U32); + msgs[msgID++] = sel.selReg(sel.reg(FAMILY_DWORD), TYPE_U32); // fake w. if (dim < 3) - msgs[3] = sel.selReg(sel.reg(FAMILY_DWORD), TYPE_U32); + msgs[msgID++] = sel.selReg(sel.reg(FAMILY_DWORD), TYPE_U32); // LOD. - msgs[4] = sel.selReg(sel.reg(FAMILY_DWORD), TYPE_U32); - for(uint32_t msgID = dim + 2; valueID < insn.getSrcNum(); msgID++, valueID++) + msgs[msgID++] = sel.selReg(sel.reg(FAMILY_DWORD), TYPE_U32); + for(; valueID < insn.getSrcNum(); msgID++, valueID++) msgs[msgID] = sel.selReg(insn.getSrc(valueID), insn.getSrcType()); } diff --git a/backend/src/ir/instruction.cpp b/backend/src/ir/instruction.cpp index a2bc8750..797552fc 100644 --- a/backend/src/ir/instruction.cpp +++ b/backend/src/ir/instruction.cpp @@ -522,10 +522,13 @@ namespace ir { this->outOpcode(out); out << "." << this->getDstType() << "." << this->getSrcType() - << " surface id " << (int)this->getImageIndex() - << " coord u %" << this->getSrc(fn, 0) - << " coord v %" << this->getSrc(fn, 1) - << " coord w %" << this->getSrc(fn, 2) + << " surface id " << (int)this->getImageIndex(); + out << " coord u %" << this->getSrc(fn, 0); + if (srcNum >= 2) + out << " coord v %" << this->getSrc(fn, 1); + if (srcNum >= 3) + out << " coord w %" << this->getSrc(fn, 2); + out << " %" << this->getDst(fn, 0) << " %" << this->getDst(fn, 1) << " %" << this->getDst(fn, 2) @@ -567,15 +570,18 @@ namespace ir { INLINE bool wellFormed(const Function &fn, std::string &why) const; INLINE void out(std::ostream &out, const Function &fn) const { this->outOpcode(out); + uint32_t srcID = 0; out << "." << this->getSrcType() << " surface id " << (int)this->getImageIndex() - << " coord u %" << this->getSrc(fn, 0) - << " coord v %" << this->getSrc(fn, 1) - << " coord w %" << this->getSrc(fn, 2) - << " %" << this->getSrc(fn, 3) - << " %" << this->getSrc(fn, 4) - << " %" << this->getSrc(fn, 5) - << " %" << this->getSrc(fn, 6); + << " coord u %" << this->getSrc(fn, srcID++); + if (srcNum >= 6) + out << " coord v %" << this->getSrc(fn, srcID++); + if (srcNum >= 7) + out << " coord w %" << this->getSrc(fn, srcID++); + out << " %" << this->getSrc(fn, srcID++); + out << " %" << this->getSrc(fn, srcID++); + out << " %" << this->getSrc(fn, srcID++); + out << " %" << this->getSrc(fn, srcID++); } Tuple src; |