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2017-10-02meson: Distribute meson build system filesPetri Latvala1-0/+1
Signed-off-by: Petri Latvala <petri.latvala@intel.com> Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2017-09-18meson: Install the (dis)assemblerVille Syrjälä1-4/+17
Install the assembler and disassemebler binaries, and the accompanying pkg-config file. Change libbrw into a static library since we don't want to install that. Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
2017-09-08meson: basic build system supportDaniel Vetter1-0/+73
Why? Because it's fast. Like really, really fast. Some data (from a snb laptop, so rather lower-powered): - Incremental build after $ touch lib/igt_core.c with meson: 0.6s It notices that the symbol list of the libigt.so hasn't changed and doesn't bother re-linking the almost 300 binaries we have. make -j 6 for the same scenario takes 44s. - Incremental build with nothing changed: make: 0.7s, meson: 0.2s This means stuff like --disable-git-hash is entirely pointless with meson, it's faster than a make ever can be (with 0.6s). - Reconfigure stage: ninja reconfigure 0.8s vs. ./configure 8.6s) - Running tests, after a full build: ninja test 6s vs. make check 24s - Full build (i.e. including ./autogen.sh respectively meson build), including tests, from a pristine git checkout. automake 2m49s vs. meson 44s. Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Eric Anholt <eric@anholt.net> Cc: Daniel Stone <daniel@fooishbar.org> Acked-by: Jani Nikula <jani.nikula@intel.com> Acked-by: Arkadiusz Hiler <arkadiusz.hiler@intel.com> Acked-by: Petri Latvala <petri.latvala@intel.com> Acked-by: Daniel Stone <daniels@collabora.com> Acked-by: Radoslaw Szwichtenberg <radoslaw.szwichtenberg@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
2017-09-08assembler/test: Prep work for mesonDaniel Vetter1-4/+12
Again we want to be able to run each testcase individually. Also, we need to make sure the target directory for the temp files exists - meson always builds with a build-dir outside of the source tree. Acked-by: Jani Nikula <jani.nikula@intel.com> Acked-by: Arkadiusz Hiler <arkadiusz.hiler@intel.com> Acked-by: Petri Latvala <petri.latvala@intel.com> Acked-by: Daniel Stone <daniels@collabora.com> Acked-by: Radoslaw Szwichtenberg <radoslaw.szwichtenberg@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2017-03-10assembler/gen8_disasm.c: Remove unused m_mask_ctrlPetri Latvala1-5/+0
Signed-off-by: Petri Latvala <petri.latvala@intel.com> Reviewed-by: Mika Kahola <mika.kahola@intel.com>
2016-11-30assembler: RSQ is a math functionKristian H. Kristensen1-1/+1
Signed-off-by: Kristian H. Kristensen <hoegsberg@gmail.com> Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2016-11-30assembler: Set 3src options before sourcesKristian H. Kristensen1-1/+1
Setting the 3src sources will assert align16, but that doesn't get set until we call set_instruction_options(). Call that before setting sources. Signed-off-by: Kristian H. Kristensen <hoegsberg@gmail.com> Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2016-11-30assembler: Fix assert when setting 3src sourcesKristian H. Kristensen1-2/+2
We need to map the type to the 3src encoding before comparing to insn->bits1.da3src.src_reg_type, which is 3src encoded. Signed-off-by: Kristian H. Kristensen <hoegsberg@gmail.com> Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2016-09-01autotools/: Allow check target to be invoked w/o the need to issue a build.Marius Vlad3-96/+107
We need to have the test list generated before running the check target. Migrated igt_command_line.sh to tests/ from lib/tests/, which allows to building the tests and execute the script. This would allow cleaning followed by a make check. Also assembler/ directory needs also to be adjusted in order for this to work. Kept the possibility to invoke tests/igt_command_line.sh to determine which test is failing. Signed-off-by: Marius Vlad <marius.c.vlad@intel.com> Url: https://patchwork.freedesktop.org/series/6539/ Reviewed-By: Chris Wilson <chris@chris-wilson.co.uk>
2016-06-23assembler/: Fix lex warnings for %empty and %nonassoc.marius vlad1-37/+37
Signed-off-by: Marius Vlad <marius.c.vlad@intel.com> Acked-by: Damien Lespiau <damien.lespiau@intel.com>
2015-08-21assembler: remove built sources with make cleanThomas Wood1-1/+1
Built sources are generated by "make all", so should be removed by "make clean". This also ensures "distcleancheck" passes. Signed-off-by: Thomas Wood <thomas.wood@intel.com>
2014-09-30assembler/skl: update the extdesc field for SEND instructionZhao Yakui4-2/+38
The send instruction on gen9 uses the 32bit immediate instead of 6bit immediate for the extended message descriptors. And some bits of SEND instruction are defined as the extdesc field. Signed-off-by: Zhao Yakui <yakui.zhao@intel.com> Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2014-09-30assembler/skl: Add more cache agent for write(...)Zhao Yakui1-10/+30
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com> Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2014-09-30assembler/skl: update read(...)Zhao Yakui1-1/+21
READ(...) is used for Render Target read and Media Block read. But there is no sampler cache agent on gen9. At the same time two message types don't share the same cache agent any more. So a parameter is needed for cache agent. The 2th parameter of read(...) is not used for gen6/gen7/gen8. Hence it is reused as cache agent for SKL as that on ILK. Signed-off-by: Zhao Yakui <yakui.zhao@intel.com> Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2014-09-30assembler/skl: Redefine the cache agent type for some fixed functionsZhao Yakui1-0/+7
The different cache agent type is defined for SKL although it still uses the same function ID as the previous generations. Signed-off-by: Zhao Yakui <yakui.zhao@intel.com> Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2014-09-30assembler/skl: Add gen 9 to the -g optionDamien Lespiau2-4/+4
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Ben Widawsky <ben@bwidawsk.net> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2014-05-19assembler: distinguish the channel of .z from the condition of .zXiang, Haihao1-0/+45
The scratch patch only works for generic register Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=75631 Tested-by: Matt Turner <mattst88@gmail.com> Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2014-05-19assembler: switch the order of swizzle and regtype to match the BNF of the ↵Xiang, Haihao1-3/+3
assembly Fortunately our existing source didn't use swizzle. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=75631 Tested-by: Matt Turner <mattst88@gmail.com> Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2014-02-13Assembler/bdw: Remove the unsupported cache agent for WRITE(...)Zhao Yakui1-4/+0
The Sampler/Constant cache is read-only. And it can't be used as the target cache agent of WRITE message. Reviewed-by: Xiang, Haihao <haihao.xiang@intel.com> Signed-off-by: Zhao Yakui <yakui.zhao@intel.com> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2014-02-11assembler: fix condition for printing a warningThomas Wood1-1/+1
Signed-off-by: Thomas Wood <thomas.wood@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-02-06assembler: define YY_NO_INPUT to prevent unused symbol warningsThomas Wood1-0/+1
Signed-off-by: Thomas Wood <thomas.wood@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-12-06assembler/bdw: Update write(...)Xiang, Haihao1-2/+28
write(...) is used for Render Target Write and Media Block Write. The two message types no longer share the same cache agent on GEN8, So a parameter is needed for cache agent. The 4th parameter of write() is used for write commit bit which has been removed since GEN7. Hence we can re-use the 4th parameter as cache agent on GEN8 Reviewed-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2013-11-06assembler/bdw: Add the DATA_PORT_CACHE1 shared function for Gen8+Zhao Yakui2-1/+3
This is required to send some messages to data port in GPU shader. For example: media_block_write message. Signed-off-by: Zhao Yakui <yakui.zhao@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
2013-11-06assembler/bdw: Add the support of align1 register-indirect addressing mode ↵Zhao Yakui3-15/+101
on Gen8 Otherwise it can't compile the following GPU shader that uses the register-indirect addressing mode. >add.sat (16) r[a0.5,0]<1>:uw r[a0.5,0]<16;16,1>:uw 0x0080:uw >add.sat (16) r[a0.5,32]<1>:uw r[a0.5,32]<16;16,1>:uw 0x0080:uw Signed-off-by: Zhao Yakui <yakui.zhao@intel.com> Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
2013-11-06assembler/bdw: SEND instructionXiang, Haihao1-4/+15
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com> Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
2013-11-06assembler/bdw: Small cleanupBen Widawsky1-3/+1
This was originally part of: commit 62298329350b965e4bbfc558e5a4b1b3646742ea Author: Xiang, Haihao <haihao.xiang@intel.com> Date: Wed Aug 14 14:21:16 2013 -0700 assembler: error for the wrong syntax of SEND instruction on GEN6+ I merged that patch separately, but this tiny hunk was leftover. In order to not muck in changing too much history, I am leaving this as a discrete patch, but with the changed commit message Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
2013-11-06assembler/bdw: Check & Refinement Engine messageXiang, Haihao2-7/+22
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com> Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
2013-11-06assembler/bdw: Video Motion Estimation(VME) messageXiang, Haihao2-1/+14
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com> Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
2013-11-06assembler/bdw: Thread Spawn messageXiang, Haihao2-12/+29
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com> Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
2013-11-06assembler/bdw: Data port messageXiang, Haihao2-32/+80
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com> Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
2013-11-06assembler/bdw: Set thread switch for multiple branch instructionsXiang, Haihao1-2/+8
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com> Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
2013-11-06assembler/bdw: Set jip/uip offsets used by flow control instructionsXiang, Haihao2-47/+88
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com> Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
2013-11-06assembler/bdw: Disable mask control for advanced modeXiang, Haihao1-2/+6
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com> Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
2013-11-06assembler/bdw: Set math functionXiang, Haihao1-1/+6
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com> Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
2013-11-06assembler/bdw: Use gen8_set_exec_size() to set the execution sizeDamien Lespiau1-5/+13
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
2013-11-06assembler/bdw: Preliminary gen8 send & msgtarget supportDamien Lespiau1-6/+28
Still some work needed there, but enough for rendercopy. Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
2013-11-06assembler/bdw: Add the start of a gen8 disassemblerDamien Lespiau3-3/+1002
Directly taken from Mesa. v2 (Ben): Updated copyright Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
2013-11-06assembler/bdw: Make the validation functions take a brw_program_instructionDamien Lespiau1-10/+26
This allows to use the same functions to validate operands on gen8 for now. Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
2013-11-06assembler/bdw: Support some basic gen8 intructionsDamien Lespiau2-8/+60
We should now support alu2 intructions with direct register addressing. Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
2013-11-06assembler/bdw: Add gen8_instruction from mesaDamien Lespiau5-2/+681
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
2013-11-04Update .gitignore a bitDaniel Vetter1-4/+5
- Ignore build-aux/ - Cleanup ignores for assembler/
2013-08-20assembler: Disable the declare testDamien Lespiau1-1/+1
It's not hitting a valid assertion that it tries to write an instruction without a defined execution size (because the "default" exec_size never end up being set). Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2013-08-20assembler: Disable tests that where already failing in the gen4asm repoDamien Lespiau1-5/+13
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2013-08-20assembler: Ignore make check outputDamien Lespiau1-0/+3
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2013-08-20assembler: Fix the path of intel-gen4asmDamien Lespiau1-1/+1
With the move to intel-gpu-tools, we need to update that as well. Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2013-08-20assembler: Revert "Fix missing environment variables problem in ↵Damien Lespiau1-7/+5
test/run-test.sh" Same as: commit 497814f2f2828efdc5bdd787ebc490d5083f61b8 Author: Damien Lespiau <damien.lespiau@intel.com> Date: Tue Aug 20 14:52:05 2013 +0100 assembler: Revert "Automatically run all test cases." make check will define srcdir and buildir variables for us. This reverts commit 1c009349bc894bd195b5522540536898b0bee574.
2013-08-20assembler: Revert "Automatically run all test cases."Damien Lespiau2-80/+11
The tests where supposed to be run through make check, not running the "run-test.sh" standalone. So revert that patch to have make check work as intended. This reverts commit 6983eebf47f37def8f2315d5af1800b81644f240.
2013-08-20assembler: Tune the error message for invalid send on gen6+Damien Lespiau1-6/+6
And be a bit more descriptive. Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2013-08-15assembler: error for the wrong syntax of SEND instruction on GEN6+Xiang, Haihao1-0/+12
predicate SEND execsize dst sendleadreg payload directsrcoperand instoptions predicate SEND execsize dst sendleadreg payload imm32reg instoptions predicate SEND execsize dst sendleadreg payload sndopr imm32reg instoptions predicate SEND execsize dst sendleadreg payload exp directsrcoperand instoptions The above four syntaxes are only used on legacy platforms which support implied move from payload to dst. Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com> Reviewed-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
2013-05-22assembler: Add support for the SENDC instruction.Matt Turner2-8/+13
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
generated by cgit v1.2.3 (git 2.39.1) at 2024-06-04 17:07:21 +0000