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authoraurel32 <aurel32@c046a42c-6fe2-441c-8c8c-71466251a162>2009-03-03 06:12:03 +0000
committeraurel32 <aurel32@c046a42c-6fe2-441c-8c8c-71466251a162>2009-03-03 06:12:03 +0000
commitef7ec1c16d184c6b7296d681aaa7e4f37cb57c6c (patch)
tree9f70aef16c0acde2e6e226a2b3019ef431388aac /target-sh4
parent8dd640e49daeba4a47c1f9e75e0f09aeb5578644 (diff)
clean build: Fix remaining sh4 warnings
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6668 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-sh4')
-rw-r--r--target-sh4/cpu.h2
-rw-r--r--target-sh4/exec.h6
-rw-r--r--target-sh4/helper.c14
3 files changed, 9 insertions, 13 deletions
diff --git a/target-sh4/cpu.h b/target-sh4/cpu.h
index 7ee22d89e..c0215f8ae 100644
--- a/target-sh4/cpu.h
+++ b/target-sh4/cpu.h
@@ -165,6 +165,8 @@ static inline void cpu_set_tls(CPUSH4State *env, target_ulong newtls)
env->gbr = newtls;
}
+void cpu_load_tlb(CPUSH4State * env);
+
#include "softfloat.h"
#define CPUState CPUSH4State
diff --git a/target-sh4/exec.h b/target-sh4/exec.h
index e74dc9d36..ad26990c5 100644
--- a/target-sh4/exec.h
+++ b/target-sh4/exec.h
@@ -53,10 +53,4 @@ static inline void env_to_regs(void)
/* XXXXX */
}
-void cpu_load_tlb(CPUState * env);
-
-int find_itlb_entry(CPUState * env, target_ulong address,
- int use_asid, int update);
-int find_utlb_entry(CPUState * env, target_ulong address, int use_asid);
-
#endif /* _EXEC_SH4_H */
diff --git a/target-sh4/helper.c b/target-sh4/helper.c
index 7f5430abc..f1c170e3b 100644
--- a/target-sh4/helper.c
+++ b/target-sh4/helper.c
@@ -313,8 +313,8 @@ static void increment_urc(CPUState * env)
Return entry, MMU_ITLB_MISS, MMU_ITLB_MULTIPLE or MMU_DTLB_MULTIPLE
Update the itlb from utlb if update is not 0
*/
-int find_itlb_entry(CPUState * env, target_ulong address,
- int use_asid, int update)
+static int find_itlb_entry(CPUState * env, target_ulong address,
+ int use_asid, int update)
{
int e, n;
@@ -344,7 +344,7 @@ int find_itlb_entry(CPUState * env, target_ulong address,
/* Find utlb entry
Return entry, MMU_DTLB_MISS, MMU_DTLB_MULTIPLE */
-int find_utlb_entry(CPUState * env, target_ulong address, int use_asid)
+static int find_utlb_entry(CPUState * env, target_ulong address, int use_asid)
{
/* per utlb access */
increment_urc(env);
@@ -418,9 +418,9 @@ static int get_mmu_address(CPUState * env, target_ulong * physical,
return n;
}
-int get_physical_address(CPUState * env, target_ulong * physical,
- int *prot, target_ulong address,
- int rw, int access_type)
+static int get_physical_address(CPUState * env, target_ulong * physical,
+ int *prot, target_ulong address,
+ int rw, int access_type)
{
/* P1, P2 and P4 areas do not use translation */
if ((address >= 0x80000000 && address < 0xc0000000) ||
@@ -525,7 +525,7 @@ target_phys_addr_t cpu_get_phys_page_debug(CPUState * env, target_ulong addr)
return physical;
}
-void cpu_load_tlb(CPUState * env)
+void cpu_load_tlb(CPUSH4State * env)
{
int n = cpu_mmucr_urc(env->mmucr);
tlb_t * entry = &env->utlb[n];