diff options
| -rw-r--r-- | include/llvm/IR/IntrinsicsTGSI.td | 2 | ||||
| -rw-r--r-- | lib/Target/TGSI/TGSIISelLowering.cpp | 3 | ||||
| -rw-r--r-- | lib/Target/TGSI/TGSIRegisterInfo.cpp | 6 | ||||
| -rw-r--r-- | lib/Target/TGSI/TGSIRegisterInfo.h | 4 | ||||
| -rw-r--r-- | lib/Target/TGSI/TGSIRegisterInfo.td | 11 |
5 files changed, 22 insertions, 4 deletions
diff --git a/include/llvm/IR/IntrinsicsTGSI.td b/include/llvm/IR/IntrinsicsTGSI.td index 1bb6c9b6309..d796de8e0e7 100644 --- a/include/llvm/IR/IntrinsicsTGSI.td +++ b/include/llvm/IR/IntrinsicsTGSI.td @@ -31,5 +31,7 @@ defm int_tgsi_read_gridsize : TGSIReadPreloadRegisterIntrinsic_xyz < "__builtin_tgsi_read_gridsize">; defm int_tgsi_read_threadid : TGSIReadPreloadRegisterIntrinsic_xyz < "__builtin_tgsi_read_threadid">; +def int_tgsi_read_workdim : TGSIReadPreloadRegisterIntrinsic < + "__builtin_tgsi_read_workdim">; } // End TargetPrefix = "tgsi" diff --git a/lib/Target/TGSI/TGSIISelLowering.cpp b/lib/Target/TGSI/TGSIISelLowering.cpp index 2728164cf1c..77187bff8e2 100644 --- a/lib/Target/TGSI/TGSIISelLowering.cpp +++ b/lib/Target/TGSI/TGSIISelLowering.cpp @@ -305,6 +305,9 @@ LowerOperation(SDValue op, SelectionDAG &dag) const { case Intrinsic::tgsi_read_threadid_z: return CreateLiveInRegister(dag, &TGSI::IRegsRegClass, TGSI_THREAD_ID(z), VT); + case Intrinsic::tgsi_read_workdim: + return CreateLiveInRegister(dag, &TGSI::IRegsRegClass, + TGSI_WORK_DIM, VT); default: llvm_unreachable("Unknown TGSI Intrinsic"); } diff --git a/lib/Target/TGSI/TGSIRegisterInfo.cpp b/lib/Target/TGSI/TGSIRegisterInfo.cpp index f849d490469..6b41e08d77a 100644 --- a/lib/Target/TGSI/TGSIRegisterInfo.cpp +++ b/lib/Target/TGSI/TGSIRegisterInfo.cpp @@ -80,6 +80,12 @@ BitVector TGSIRegisterInfo::getReservedRegs(const MachineFunction &MF) const { rsv.set(TGSI::SV3w); rsv.set(TGSI::SV3); + rsv.set(TGSI::SV4x); + rsv.set(TGSI::SV4y); + rsv.set(TGSI::SV4z); + rsv.set(TGSI::SV4w); + rsv.set(TGSI::SV4); + rsv.set(TGSI::ADDR0x); rsv.set(TGSI::ADDR0y); rsv.set(TGSI::ADDR0z); diff --git a/lib/Target/TGSI/TGSIRegisterInfo.h b/lib/Target/TGSI/TGSIRegisterInfo.h index e9c6309c9fe..2a7f2a18650 100644 --- a/lib/Target/TGSI/TGSIRegisterInfo.h +++ b/lib/Target/TGSI/TGSIRegisterInfo.h @@ -23,12 +23,14 @@ "DCL SV[0], BLOCK_ID[0]\n" \ "DCL SV[1], BLOCK_SIZE[0]\n" \ "DCL SV[2], GRID_SIZE[0]\n" \ - "DCL SV[3], THREAD_ID[0]\n" + "DCL SV[3], THREAD_ID[0]\n" \ + "DCL SV[4], WORK_DIM[0]\n" #define TGSI_BLOCK_ID(suffix) TGSI::SV0 ## suffix #define TGSI_BLOCK_SIZE(suffix) TGSI::SV1 ## suffix #define TGSI_GRID_SIZE(suffix) TGSI::SV2 ## suffix #define TGSI_THREAD_ID(suffix) TGSI::SV3 ## suffix +#define TGSI_WORK_DIM TGSI::SV4x // These needs to be kept in sync with the LD/ST definitions in TGSIInstrInfo.td #define TGSI_MEM_DECL \ diff --git a/lib/Target/TGSI/TGSIRegisterInfo.td b/lib/Target/TGSI/TGSIRegisterInfo.td index 8f19945079a..f5581ebb90c 100644 --- a/lib/Target/TGSI/TGSIRegisterInfo.td +++ b/lib/Target/TGSI/TGSIRegisterInfo.td @@ -213,6 +213,11 @@ def SV3y : TGSIReg<"SV[3].y", 3, 2>; def SV3z : TGSIReg<"SV[3].z", 3, 4>; def SV3w : TGSIReg<"SV[3].w", 3, 8>; def SV3 : TGSIVReg<"SV[3]", 3, [SV3x, SV3y, SV3z, SV3w]>; +def SV4x : TGSIReg<"SV[4].x", 4, 1>; +def SV4y : TGSIReg<"SV[4].y", 4, 2>; +def SV4z : TGSIReg<"SV[4].z", 4, 4>; +def SV4w : TGSIReg<"SV[4].w", 4, 8>; +def SV4 : TGSIVReg<"SV[4]", 4, [SV4x, SV4y, SV4z, SV4w]>; // Address register def ADDR0x : TGSIReg<"ADDR0x", 0, 1>; @@ -226,10 +231,10 @@ def ADDR0 : TGSIVReg<"ADDR0", 0, [ADDR0x, ADDR0y, ADDR0z, ADDR0w]>; def IRegs : RegisterClass<"TGSI", [i32], 32, (add (sequence "TEMP%ux", 0, 31), (sequence "TEMP%uy", 0, 31), (sequence "TEMP%uz", 0, 31), (sequence "TEMP%uw", 0, 31), - (sequence "SV%ux", 0, 3), (sequence "SV%uy", 0, 3), - (sequence "SV%uz", 0, 3), (sequence "SV%uw", 0, 3))>; + (sequence "SV%ux", 0, 4), (sequence "SV%uy", 0, 4), + (sequence "SV%uz", 0, 4), (sequence "SV%uw", 0, 4))>; def IVRegs : RegisterClass<"TGSI", [v4i32], 128, - (add (sequence "TEMP%u", 0, 31), (sequence "SV%u", 0, 3))>; + (add (sequence "TEMP%u", 0, 31), (sequence "SV%u", 0, 4))>; def FRegs : RegisterClass<"TGSI", [f32], 32, (add (sequence "TEMP%ux", 0, 31), (sequence "TEMP%uy", 0, 31), (sequence "TEMP%uz", 0, 31), (sequence "TEMP%uw", 0, 31))>; |