diff options
author | Simon Dardis <simon.dardis@imgtec.com> | 2016-06-23 09:22:11 +0000 |
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committer | Simon Dardis <simon.dardis@imgtec.com> | 2016-06-23 09:22:11 +0000 |
commit | 53391f414b89a1bd55143e7af5dc84002bc22db8 (patch) | |
tree | cdc67ad20497789e8accfec95fb39bc4d984e5ee /include | |
parent | a4a23eae96a0167e5607b12afe1abdaaf36a1465 (diff) |
[misched] Extend scheduler to handle unsupported features
Currently isComplete = 1 requires that every instruction must
be described, declared unsupported or marked as having no
scheduling information for a processor.
For some backends such as MIPS, this requirement entails
long regex lists of instructions that are unsupported.
This patch teaches Tablegen to skip over instructions that
are associated with unsupported feature when checking if the
scheduling model is complete.
Patch by: Daniel Sanders
Contributions by: Simon Dardis
Reviewers: MatzeB
Differential Reviewer: http://reviews.llvm.org/D20522
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@273551 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'include')
-rw-r--r-- | include/llvm/Target/TargetSchedule.td | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/include/llvm/Target/TargetSchedule.td b/include/llvm/Target/TargetSchedule.td index 7f92e8b6556..74b98ac5f6c 100644 --- a/include/llvm/Target/TargetSchedule.td +++ b/include/llvm/Target/TargetSchedule.td @@ -55,6 +55,8 @@ include "llvm/Target/TargetItinerary.td" class Instruction; // Forward def +class Predicate; // Forward def + // DAG operator that interprets the DAG args as Instruction defs. def instrs; @@ -97,6 +99,20 @@ class SchedMachineModel { // resulting from changes to the instruction definitions. bit CompleteModel = 1; + // A processor may only implement part of published ISA, due to either new ISA + // extensions, (e.g. Pentium 4 doesn't have AVX) or implementation + // (ARM/MIPS/PowerPC/SPARC soft float cores). + // + // For a processor which doesn't support some feature(s), the schedule model + // can use: + // + // let<Predicate> UnsupportedFeatures = [HaveA,..,HaveY]; + // + // to skip the checks for scheduling information when building LLVM for + // instructions which have any of the listed predicates in their Predicates + // field. + list<Predicate> UnsupportedFeatures = []; + bit NoModel = 0; // Special tag to indicate missing machine model. } |