diff options
| author | Joakim Sindholt <opensource@zhasha.com> | 2009-10-15 07:48:30 +0200 |
|---|---|---|
| committer | Joakim Sindholt <opensource@zhasha.com> | 2009-10-15 07:48:30 +0200 |
| commit | cd56eb7c3f543899965a2e87d9817fe0f3fd0b5b (patch) | |
| tree | 73c271547a9e2e39ee354189aa77743875c1925d | |
| parent | f7987d022815989027b4014e25e3e0c03ffb260d (diff) | |
xml: regenerate for the last time
| -rw-r--r-- | r300reg.xml | 1017 |
1 files changed, 388 insertions, 629 deletions
diff --git a/r300reg.xml b/r300reg.xml index 121f5a7..9d13bd9 100644 --- a/r300reg.xml +++ b/r300reg.xml @@ -15,8 +15,8 @@ <value value="1" name="ADD_BUT_NO_CLAMP"><doc>Add but no Clamp</doc></value> <value value="2" name="SUBTRACT_DST_FROM_SRC"><doc>Subtract Dst from Src, and Clamp</doc></value> <value value="3" name="SUBTRACT_DST_FROM_SRC"><doc>Subtract Dst from Src, and don`t Clamp</doc></value> - <value value="4" name="MINIMUM_OF_SRC"><doc>Minimum of Src, Dst (the src and dst blend</doc></value> - <value value="5" name="MAXIMUM_OF_SRC"><doc>Maximum of Src, Dst (the src and dst blend</doc></value> + <value value="4" name="MINIMUM_OF_SRC"><doc>Minimum of Src, Dst (the src and dst blend functions are forced to D3D_ONE)</doc></value> + <value value="5" name="MAXIMUM_OF_SRC"><doc>Maximum of Src, Dst (the src and dst blend functions are forced to D3D_ONE)</doc></value> <value value="6" name="SUBTRACT_SRC_FROM_DST"><doc>Subtract Src from Dst, and Clamp</doc></value> <value value="7" name="SUBTRACT_SRC_FROM_DST"><doc>Subtract Src from Dst, and don`t Clamp</doc></value> </enum> @@ -80,6 +80,12 @@ <value value="0" name="DISABLE"><doc>Disable</doc></value> <value value="1" name="ENABLE"><doc>Enable</doc></value> </enum> +<enum name="ENUM7"> + <value value="0" name="1_BUFFER"><doc>1 buffer. This is the only mode where the cb processes the end of packet command.</doc></value> + <value value="1" name="2_BUFFERS"><doc>2 buffers</doc></value> + <value value="2" name="3_BUFFERS"><doc>3 buffers</doc></value> + <value value="3" name="4_BUFFERS"><doc>4 buffers</doc></value> +</enum> <enum name="ENUM8"> <value value="0" name="3D_DESTINATION_IS_NOT_MACROTILED"><doc>3D destination is not macrotiled</doc></value> <value value="1" name="3D_DESTINATION_IS_MACROTILED"><doc>3D destination is macrotiled</doc></value> @@ -87,7 +93,7 @@ <enum name="ENUM9"> <value value="0" name="3D_DESTINATION_IS_NO_MICROTILED"><doc>3D destination is no microtiled</doc></value> <value value="1" name="3D_DESTINATION_IS_MICROTILED"><doc>3D destination is microtiled</doc></value> - <value value="2" name="3D_DESTINATION_IS_SQUARE_MICROTILED"><doc>3D destination is square microtiled. Only</doc></value> + <value value="2" name="3D_DESTINATION_IS_SQUARE_MICROTILED"><doc>3D destination is square microtiled. Only available in 16-bit</doc></value> </enum> <enum name="ENUM10"> <value value="0" name="NO_SWAP"><doc>No swap</doc></value> @@ -121,16 +127,16 @@ </enum> <enum name="ENUM22"> <value value="0" name="NO_EFFECT"><doc>No effect.</doc></value> - <value value="1" name="PREVENTS_TCL_INTERFACE_FROM_DEADLOCKING_ON_GA"><doc>Prevents TCL interface from deadlocking on GA</doc></value> + <value value="1" name="PREVENTS_TCL_INTERFACE_FROM_DEADLOCKING_ON_GA_SIDE"><doc>Prevents TCL interface from deadlocking on GA side.</doc></value> </enum> <enum name="ENUM23"> <value value="0" name="NO_EFFECT"><doc>No effect.</doc></value> - <value value="1" name="ENABLES_HIGH"><doc>Enables high-performance register/primitive</doc></value> + <value value="1" name="ENABLES_HIGH"><doc>Enables high-performance register/primitive switching.</doc></value> </enum> <enum name="ENUM24"> <value value="0" name="HORIZONTAL"><doc>Horizontal</doc></value> <value value="1" name="VERTICAL"><doc>Vertical</doc></value> - <value value="2" name="SQUARE"><doc>Square (horizontal or vertical depending upon</doc></value> + <value value="2" name="SQUARE"><doc>Square (horizontal or vertical depending upon slope)</doc></value> <value value="3" name="COMPUTED"><doc>Computed (perpendicular to slope)</doc></value> </enum> <enum name="ENUM27"> @@ -144,7 +150,7 @@ </enum> <enum name="ENUM32"> <value value="0" name="DISABLE_STENCIL_AUTO_INC"><doc>Disable stencil auto inc/dec (def).</doc></value> - <value value="1" name="ENABLE_STENCIL_AUTO_INC"><doc>Enable stencil auto inc/dec based on triangle</doc></value> + <value value="1" name="ENABLE_STENCIL_AUTO_INC"><doc>Enable stencil auto inc/dec based on triangle cw/ccw, force into dzy low bit.</doc></value> <value value="2" name="FORCE_0_INTO_DZY_LOW_BIT"><doc>Force 0 into dzy low bit.</doc></value> </enum> <enum name="ENUM41"> @@ -211,7 +217,7 @@ </enum> <enum name="ENUM55"> <value value="0" name="SAMPLE_TEXTURE_COORDINATES_AT_REAL_PIXEL_CENTERS"><doc>Sample texture coordinates at real pixel centers</doc></value> - <value value="1" name="SAMPLE_TEXTURE_COORDINATES_AT_ADJUSTED_PIXEL"><doc>Sample texture coordinates at adjusted pixel</doc></value> + <value value="1" name="SAMPLE_TEXTURE_COORDINATES_AT_ADJUSTED_PIXEL_CENTERS"><doc>Sample texture coordinates at adjusted pixel centers</doc></value> </enum> <enum name="ENUM57"> <value value="0" name="FOUR_COMPONENTS"><doc>Four components (R,G,B,A)</doc></value> @@ -320,14 +326,14 @@ <value value="2" name="LINEAR"><doc>Linear</doc></value> </enum> <enum name="ENUM72"> - <value value="0" name="NONE"><doc>None (no filter specifed, select from MIN/MAG</doc></value> + <value value="0" name="NONE"><doc>None (no filter specifed, select from MIN/MAG filters)</doc></value> <value value="1" name="POINT"><doc>Point</doc></value> <value value="2" name="LINEAR"><doc>Linear</doc></value> </enum> <enum name="ENUM73"> <value value="0" name="DISABLE"><doc>Disable</doc></value> - <value value="1" name="CHROMAKEY"><doc>ChromaKey (kill pixel if any sample matches</doc></value> - <value value="2" name="CHROMAKEYBLEND"><doc>ChromaKeyBlend (set sample to 0 if it matches</doc></value> + <value value="1" name="CHROMAKEY"><doc>ChromaKey (kill pixel if any sample matches chroma key)</doc></value> + <value value="2" name="CHROMAKEYBLEND"><doc>ChromaKeyBlend (set sample to 0 if it matches chroma key)</doc></value> </enum> <enum name="ENUM74"> <value value="0" name="NORMAL_ROUNDING_ON_ALL_COMPONENTS"><doc>Normal rounding on all components (+0.5)</doc></value> @@ -335,7 +341,7 @@ </enum> <enum name="ENUM75"> <value value="0" name="DONT_TRUNCATE_COORDINATE_FRACTIONS"><doc>Dont truncate coordinate fractions.</doc></value> - <value value="1" name="TRUNCATE_COORDINATE_FRACTIONS_TO_0"><doc>Truncate coordinate fractions to 0.0 and 0.5 for</doc></value> + <value value="1" name="TRUNCATE_COORDINATE_FRACTIONS_TO_0"><doc>Truncate coordinate fractions to 0.0 and 0.5 for MPEG</doc></value> </enum> <enum name="ENUM76"> <value value="0" name="NON"><doc>Non-Projected</doc></value> @@ -345,6 +351,11 @@ <value value="0" name="USE_TXWIDTH_FOR_IMAGE_ADDRESSING"><doc>Use TXWIDTH for image addressing</doc></value> <value value="1" name="USE_TXPITCH_FOR_IMAGE_ADDRESSING"><doc>Use TXPITCH for image addressing</doc></value> </enum> +<enum name="ENUM87"> + <value value="0" name="DISABLE_YUV_TO_RGB_CONVERSION"><doc>Disable YUV to RGB conversion</doc></value> + <value value="1" name="ENABLE_YUV_TO_RGB_CONVERSION"><doc>Enable YUV to RGB conversion (with clamp)</doc></value> + <value value="2" name="ENABLE_YUV_TO_RGB_CONVERSION"><doc>Enable YUV to RGB conversion (without clamp)</doc></value> +</enum> <enum name="ENUM88"> <value value="0" name="2D"><doc>2D</doc></value> <value value="1" name="3D"><doc>3D</doc></value> @@ -396,7 +407,7 @@ <enum name="ENUM92"> <value value="0" name="32_BYTE_CACHE_LINE_IS_LINEAR"><doc>32 byte cache line is linear</doc></value> <value value="1" name="32_BYTE_CACHE_LINE_IS_TILED"><doc>32 byte cache line is tiled</doc></value> - <value value="2" name="32_BYTE_CACHE_LINE_IS_TILED_SQUARE"><doc>32 byte cache line is tiled square (only applies to</doc></value> + <value value="2" name="32_BYTE_CACHE_LINE_IS_TILED_SQUARE"><doc>32 byte cache line is tiled square (only applies to 16-bit texel)</doc></value> </enum> <enum name="ENUM95"> <value value="0" name="A"><doc>A: Output to render target A</doc></value> @@ -610,12 +621,16 @@ <value value="0" name="UPDATE_HIERARCHICAL_Z_WITH_MAX_VALUE"><doc>Update Hierarchical Z with Max value</doc></value> <value value="1" name="UPDATE_HIERARCHICAL_Z_WITH_MIN_VALUE"><doc>Update Hierarchical Z with Min value</doc></value> </enum> -<enum name="ENUM132"> +<enum name="ENUM130"> + <value value="0" name="Z_UNIT_CACHE_CONTROLLER_DOES_RMW"><doc>Z unit cache controller does RMW</doc></value> + <value value="1" name="Z_UNIT_CACHE_CONTROLLER_DOES_CACHE"><doc>Z unit cache controller does cache-line granular Write only</doc></value> +</enum> +<enum name="ENUM133"> <value value="0" name="16"><doc>16-bit Integer Z</doc></value> <value value="1" name="16"><doc>16-bit compressed 13E3</doc></value> <value value="2" name="24"><doc>24-bit Integer Z, 8 bit Stencil (LSBs)</doc></value> </enum> -<enum name="ENUM138"> +<enum name="ENUM139"> <value value="0" name="NEVER"><doc>Never</doc></value> <value value="1" name="LESS"><doc>Less</doc></value> <value value="2" name="LESS_OR_EQUAL"><doc>Less or Equal</doc></value> @@ -625,7 +640,7 @@ <value value="6" name="NOT_EQUAL"><doc>Not Equal</doc></value> <value value="7" name="ALWAYS"><doc>Always</doc></value> </enum> -<enum name="ENUM139"> +<enum name="ENUM140"> <value value="0" name="NEVER"><doc>Never</doc></value> <value value="1" name="LESS"><doc>Less</doc></value> <value value="2" name="LESS_OR_EQUAL"><doc>Less or Equal</doc></value> @@ -635,7 +650,7 @@ <value value="6" name="NOT_EQUAL"><doc>Not Equal</doc></value> <value value="7" name="ALWAYS"><doc>Always</doc></value> </enum> -<enum name="ENUM140"> +<enum name="ENUM141"> <value value="0" name="KEEP"><doc>Keep: New value = Old value</doc></value> <value value="1" name="ZERO"><doc>Zero: New value = 0</doc></value> <value value="2" name="REPLACE"><doc>Replace: New value = STENCILREF</doc></value> @@ -645,11 +660,11 @@ <value value="6" name="INCREMENT"><doc>Increment: New value++ (wrap)</doc></value> <value value="7" name="DECREMENT"><doc>Decrement: New value-- (wrap)</doc></value> </enum> -<enum name="ENUM143"> +<enum name="ENUM144"> <value value="0" name=""><doc>>PIO,</doc></value> <value value="1" name=""><doc>>BM</doc></value> </enum> -<enum name="ENUM145"> +<enum name="ENUM146"> <value value="0" name="PHYSICAL"><doc>Physical (Default),</doc></value> <value value="1" name="VIRTUAL"><doc>Virtual</doc></value> </enum> @@ -673,7 +688,7 @@ <value value="10" name="STUFF_TEXTURE_9"><doc>Stuff texture 9/C3</doc></value> </enum> <enum name="ENUM163"> - <value value="0" name="REPLICATE_VAP_SOURCE_TEXTURE_COORDINATES"><doc>Replicate VAP source texture coordinates</doc></value> + <value value="0" name="REPLICATE_VAP_SOURCE_TEXTURE_COORDINATES"><doc>Replicate VAP source texture coordinates (S,T,[R,Q]).</doc></value> <value value="1" name="STUFF_WITH_SOURCE_TEXTURE_COORDINATES"><doc>Stuff with source texture coordinates (S,T).</doc></value> <value value="2" name="STUFF_WITH_SOURCE_TEXTURE_COORDINATES"><doc>Stuff with source texture coordinates (S,T,R).</doc></value> </enum> @@ -683,8 +698,8 @@ <value value="2" name="LINEAR"><doc>Linear</doc></value> </enum> <enum name="ENUM187"> - <value value="0" name="COMPONENT_FILTER_SHOULD_INTERPRET_TEXEL_DATA_AS"><doc>Component filter should interpret texel data as</doc></value> - <value value="1" name="COMPONENT_FILTER_SHOULD_INTERPRET_TEXEL_DATA_AS"><doc>Component filter should interpret texel data as</doc></value> + <value value="0" name="COMPONENT_FILTER_SHOULD_INTERPRET_TEXEL_DATA_AS_UNSIGNED"><doc>Component filter should interpret texel data as unsigned</doc></value> + <value value="1" name="COMPONENT_FILTER_SHOULD_INTERPRET_TEXEL_DATA_AS_SIGNED"><doc>Component filter should interpret texel data as signed</doc></value> </enum> <enum name="ENUM188"> <value value="0" name="SELECT_TEXTURE_COMPONENT0"><doc>Select Texture Component0.</doc></value> @@ -694,17 +709,17 @@ <value value="4" name="SELECT_THE_VALUE_0"><doc>Select the value 0.</doc></value> <value value="5" name="SELECT_THE_VALUE_1"><doc>Select the value 1.</doc></value> </enum> -<enum name="ENUM193"> +<enum name="ENUM192"> <value value="0" name="NONE"><doc>NONE: Do not modify destination address.</doc></value> <value value="1" name="RELATIVE"><doc>RELATIVE: Add aL to address before write.</doc></value> </enum> -<enum name="ENUM194"> +<enum name="ENUM193"> <value value="0" name="SRC0"><doc>src0</doc></value> <value value="1" name="SRC1"><doc>src1</doc></value> <value value="2" name="SRC2"><doc>src2</doc></value> <value value="3" name="SRCP"><doc>srcp</doc></value> </enum> -<enum name="ENUM195"> +<enum name="ENUM194"> <value value="0" name="RED"><doc>Red</doc></value> <value value="1" name="GREEN"><doc>Green</doc></value> <value value="2" name="BLUE"><doc>Blue</doc></value> @@ -714,7 +729,7 @@ <value value="6" name="ONE"><doc>One</doc></value> <value value="7" name="UNUSED"><doc>Unused</doc></value> </enum> -<enum name="ENUM196"> +<enum name="ENUM195"> <value value="0" name="RESULT"><doc>Result * 1</doc></value> <value value="1" name="RESULT"><doc>Result * 2</doc></value> <value value="2" name="RESULT"><doc>Result * 4</doc></value> @@ -722,27 +737,27 @@ <value value="4" name="RESULT"><doc>Result / 2</doc></value> <value value="5" name="RESULT"><doc>Result / 4</doc></value> <value value="6" name="RESULT"><doc>Result / 8</doc></value> - <value value="7" name="DISABLE_OUTPUT_MODIFIER_AND_CLAMPING"><doc>Disable output modifier and clamping (result is</doc></value> + <value value="7" name="DISABLE_OUTPUT_MODIFIER_AND_CLAMPING"><doc>Disable output modifier and clamping (result is copied exactly; only valid for MIN/MAX/CMP/CND)</doc></value> </enum> -<enum name="ENUM197"> - <value value="0" name="A"><doc>A: Output to render target A. Predicate ==</doc></value> +<enum name="ENUM196"> + <value value="0" name="A"><doc>A: Output to render target A. Predicate == (ALU)</doc></value> <value value="1" name="B"><doc>B: Output to render target B. Predicate < (ALU)</doc></value> - <value value="2" name="C"><doc>C: Output to render target C. Predicate >=</doc></value> + <value value="2" name="C"><doc>C: Output to render target C. Predicate >= (ALU)</doc></value> <value value="3" name="D"><doc>D: Output to render target D. Predicate != (ALU)</doc></value> </enum> -<enum name="ENUM199"> - <value value="0" name="TEMPORARY"><doc>TEMPORARY: Address temporary register or</doc></value> +<enum name="ENUM198"> + <value value="0" name="TEMPORARY"><doc>TEMPORARY: Address temporary register or inline constant value.</doc></value> <value value="1" name="CONSTANT"><doc>CONSTANT: Address constant register.</doc></value> </enum> -<enum name="ENUM200"> +<enum name="ENUM199"> <value value="0" name="NONE"><doc>NONE: Do not modify source address.</doc></value> <value value="1" name="RELATIVE"><doc>RELATIVE: Add aL before lookup.</doc></value> </enum> -<enum name="ENUM206"> +<enum name="ENUM205"> <value value="0" name="NORMAL_PREDICATION"><doc>Normal predication</doc></value> <value value="1" name="INVERT_THE_VALUE_OF_THE_PREDICATE"><doc>Invert the value of the predicate</doc></value> </enum> -<enum name="ENUM211"> +<enum name="ENUM210"> <value value="0" name="NONE"><doc>NONE: Do not write any output.</doc></value> <value value="1" name="R"><doc>R: Write the red channel only.</doc></value> <value value="2" name="G"><doc>G: Write the green channel only.</doc></value> @@ -752,39 +767,39 @@ <value value="6" name="GB"><doc>GB: Write the green and blue channels.</doc></value> <value value="7" name="RGB"><doc>RGB: Write the red, green, and blue channels.</doc></value> </enum> -<enum name="ENUM230"> +<enum name="ENUM229"> <value value="0" name="NONE"><doc>NONE: Do not modify source address</doc></value> <value value="1" name="RELATIVE"><doc>RELATIVE: Add aL before lookup.</doc></value> </enum> -<enum name="ENUM231"> +<enum name="ENUM230"> <value value="0" name="USE_R_CHANNEL_AS_S_COORDINATE"><doc>Use R channel as S coordinate</doc></value> <value value="1" name="USE_G_CHANNEL_AS_S_COORDINATE"><doc>Use G channel as S coordinate</doc></value> <value value="2" name="USE_B_CHANNEL_AS_S_COORDINATE"><doc>Use B channel as S coordinate</doc></value> <value value="3" name="USE_A_CHANNEL_AS_S_COORDINATE"><doc>Use A channel as S coordinate</doc></value> </enum> -<enum name="ENUM232"> +<enum name="ENUM231"> <value value="0" name="USE_R_CHANNEL_AS_T_COORDINATE"><doc>Use R channel as T coordinate</doc></value> <value value="1" name="USE_G_CHANNEL_AS_T_COORDINATE"><doc>Use G channel as T coordinate</doc></value> <value value="2" name="USE_B_CHANNEL_AS_T_COORDINATE"><doc>Use B channel as T coordinate</doc></value> <value value="3" name="USE_A_CHANNEL_AS_T_COORDINATE"><doc>Use A channel as T coordinate</doc></value> </enum> -<enum name="ENUM233"> +<enum name="ENUM232"> <value value="0" name="USE_R_CHANNEL_AS_R_COORDINATE"><doc>Use R channel as R coordinate</doc></value> <value value="1" name="USE_G_CHANNEL_AS_R_COORDINATE"><doc>Use G channel as R coordinate</doc></value> <value value="2" name="USE_B_CHANNEL_AS_R_COORDINATE"><doc>Use B channel as R coordinate</doc></value> <value value="3" name="USE_A_CHANNEL_AS_R_COORDINATE"><doc>Use A channel as R coordinate</doc></value> </enum> -<enum name="ENUM234"> +<enum name="ENUM233"> <value value="0" name="USE_R_CHANNEL_AS_Q_COORDINATE"><doc>Use R channel as Q coordinate</doc></value> <value value="1" name="USE_G_CHANNEL_AS_Q_COORDINATE"><doc>Use G channel as Q coordinate</doc></value> <value value="2" name="USE_B_CHANNEL_AS_Q_COORDINATE"><doc>Use B channel as Q coordinate</doc></value> <value value="3" name="USE_A_CHANNEL_AS_Q_COORDINATE"><doc>Use A channel as Q coordinate</doc></value> </enum> -<enum name="ENUM245"> +<enum name="ENUM244"> <value value="12" name=""><doc>[8:0];2</doc></value> <value value="56" name=""><doc>[7:0])</doc></value> </enum> -<enum name="ENUM246"> +<enum name="ENUM245"> <value value="12" name=""><doc>[23:15];2</doc></value> <value value="56" name=""><doc>[22:15])</doc></value> </enum> @@ -824,7 +839,7 @@ </reg32> <stripe offset="0x4E28" stride="0x0004" length="4"> <reg32 name="RB3D_COLOROFFSET" access="rw" offset="0x0000"> - <doc>Color Buffer Address Offset of multibuffer 0. Unpipelined.</doc> + <doc>Color Buffer Address Offset of multibuffer 0. Unpipelined.</doc> <bitfield name="COLOROFFSET" high="31" low="5"><doc>256-bit aligned 3D destination offset address. The cache must be empty before this is changed.</doc></bitfield> </reg32> </stripe> @@ -834,10 +849,7 @@ <doc>Dither mode</doc> <use-enum ref="ENUM12" /> </bitfield> - <bitfield name="ALPHA_DITHER_MODE" high="3" low="2"> - <doc></doc> - <use-enum ref="ENUM12" /> - </bitfield> + <bitfield name="ALPHA_DITHER_MODE" high="3" low="2"><use-enum ref="ENUM12" /></bitfield> </reg32> <reg32 name="RB3D_DSTCACHE_CTLSTAT" access="rw" offset="0x4E4C"> <doc>Destination Color Buffer Cache Control/Status. If the cb is in e2 mode, then a flush or free will not occur upon a write to this register, but a sync will be immediately sent if one is requested. If both DC_FLUSH and DC_FREE are zero but DC_FINISH is one, then a sync will be sent immediately -- the cb will not wait for all the previous operations to complete before sending the sync. Unpipelined except when DC_FINISH and DC_FREE are both set to zero.</doc> @@ -856,24 +868,19 @@ <value value="3" name="FREE_3D_TAGS"><doc>Free 3D tags</doc></value> </bitfield> <bitfield name="DC_FINISH" high="4" low="4"> - <doc></doc> <value value="0" name="DO_NOT_SEND_A_FINISH_SIGNAL_TO_THE_CP"><doc>do not send a finish signal to the CP</doc></value> - <value value="1" name="SEND_A_FINISH_SIGNAL_TO_THE_CP_AFTER_THE_END_OF"><doc>send a finish signal to the CP after the end of</doc></value> + <value value="1" name="SEND_A_FINISH_SIGNAL_TO_THE_CP_AFTER_THE_END_OF_OPERATION"><doc>send a finish signal to the CP after the end of operation</doc></value> </bitfield> </reg32> <reg32 name="RB3D_ROPCNTL" access="rw" offset="0x4E18"> <doc>3D ROP Control. Stalls the 2d/3d datapath until it is idle.</doc> - <bitfield name="ROP_ENABLE" high="2" low="2"> - <doc></doc> - <use-enum ref="ENUM5" /> - </bitfield> + <bitfield name="ROP_ENABLE" high="2" low="2"><use-enum ref="ENUM5" /></bitfield> <bitfield name="ROP" high="11" low="8"><doc>ROP2 code for 3D fragments. This value is replicated into 2 nibbles to form the equivalent ROP3 code to control the ROP3 logic. These are the GDI ROP2 codes.</doc></bitfield> </reg32> <reg32 name="FG_DEPTH_SRC" access="rw" offset="0x4BD8"> <doc>Where does depth come from?</doc> <bitfield name="DEPTH_SRC" high="0" low="0"> - <doc></doc> - <value value="0" name="DEPTH_COMES_FROM_SCAN_CONVERTER_AS_PLANE"><doc>Depth comes from scan converter as plane</doc></value> + <value value="0" name="DEPTH_COMES_FROM_SCAN_CONVERTER_AS_PLANE_EQUATION"><doc>Depth comes from scan converter as plane equation.</doc></value> <value value="1" name="DEPTH_COMES_FROM_SHADER_AS_FOUR_DISCRETE_VALUES"><doc>Depth comes from shader as four discrete values.</doc></value> </bitfield> </reg32> @@ -977,7 +984,7 @@ <bitfield name="POLY_MODE" high="1" low="0"> <doc>Polygon mode enable.</doc> <value value="0" name="DISABLE_POLY_MODE"><doc>Disable poly mode (render triangles).</doc></value> - <value value="1" name="DUAL_MODE"><doc>Dual mode (send 2 sets of 3 polys with specified</doc></value> + <value value="1" name="DUAL_MODE"><doc>Dual mode (send 2 sets of 3 polys with specified poly type).</doc></value> </bitfield> <bitfield name="FRONT_PTYPE" high="6" low="4"> <doc>Specifies how to render front-facing polygons.</doc> @@ -1159,7 +1166,7 @@ </reg32> <stripe offset="0x2000" stride="0x0004" length="16"> <reg32 name="VAP_PORT_DATA" access="w" offset="0x0000"> - <doc>Setup Engine Data Port 0 through 15. 1st of 16 consecutive dwords for writing vertex data</doc> + <doc>Setup Engine Data Port 0 through 15. 1st of 16 consecutive dwords for writing vertex data</doc> </reg32> </stripe> <reg32 name="VAP_PORT_DATA_IDX_128" access="w" offset="0x20B8"> @@ -1167,12 +1174,12 @@ </reg32> <stripe offset="0x2040" stride="0x0004" length="16"> <reg32 name="VAP_PORT_IDX" access="w" offset="0x0000"> - <doc>Setup Engine Index Port 0 through 15. 1st of 16 consecutive dwords for writing vertex index</doc> + <doc>Setup Engine Index Port 0 through 15. 1st of 16 consecutive dwords for writing vertex index</doc> </reg32> </stripe> <stripe offset="0x21E0" stride="0x0004" length="8"> <reg32 name="VAP_PROG_STREAM_CNTL_EXT" access="rw" offset="0x0000"> - <doc>Programmable Stream Control Extension Word 0</doc> + <doc>Programmable Stream Control Extension Word 0</doc> <bitfield name="SWIZZLE_SELECT_X_0" high="2" low="0"><doc>X-Component Swizzle Select 0 = SELECT_X 1 = SELECT_Y 2 = SELECT_Z 3 = SELECT_W 4 = SELECT_FP_ZERO (Floating Point 0.0) 5 = SELECT_FP_ONE (Floating Point 1.0) 6,7 RESERVED</doc></bitfield> <bitfield name="SWIZZLE_SELECT_Y_0" high="5" low="3"><doc>Y-Component Swizzle Select (See Above)</doc></bitfield> <bitfield name="SWIZZLE_SELECT_Z_0" high="8" low="6"><doc>Z-Component Swizzle Select (See Above)</doc></bitfield> @@ -1226,7 +1233,7 @@ </reg32> <stripe offset="0x2230" stride="0x0004" length="16"> <reg32 name="VAP_PVS_FLOW_CNTL_ADDRS" access="rw" offset="0x0000"> - <doc>Programmable Vertex Shader Flow Control Addresses Register 0</doc> + <doc>Programmable Vertex Shader Flow Control Addresses Register 0</doc> <bitfield name="PVS_FC_ACT_ADRS_0" high="7" low="0"><doc>This field defines the last PVS instruction to execute prior to the control flow redirection. JUMP - The last instruction executed prior to the jump LOOP - The last instruction executed prior to the loop (init loop counter/inc) JSR - The last instruction executed prior to the jump to the subroutine.</doc></bitfield> <bitfield name="PVS_FC_LOOP_CNT_JMP_INST_0" high="15" low="8"><doc>This field has multiple definitions as follows: JUMP - The instruction address to jump to. LOOP - The loop count. *Note loop count of 0 must be replaced by a jump. JSR - The instruction address to jump to (first inst of subroutine).</doc></bitfield> <bitfield name="PVS_FC_LAST_INST_0" high="23" low="16"><doc>This field has multiple definitions as follows: JUMP - Not Applicable LOOP - The last instruction of the loop. JSR - The last instruction of the subroutine.</doc></bitfield> @@ -1262,7 +1269,6 @@ <doc>128-bit data path to write to Vector Memory. Used for PVS code and Constant updates.</doc> </reg32> <reg32 name="VAP_PVS_VECTOR_INDX_REG" access="rw" offset="0x2200"> - <doc></doc> <bitfield name="OCTWORD_OFFSET" high="10" low="0"><doc>Octword offset to begin writing.</doc></bitfield> </reg32> <reg32 name="VAP_PVS_VTX_TIMEOUT_REG" access="rw" offset="0x2288"> @@ -1309,13 +1315,13 @@ </reg32> <stripe offset="0x20C8" stride="0x0005" length="16"> <reg32 name="VAP_VTX_AOS_ADDR" access="rw" offset="0x0000"> - <doc>Array-of-Structures Address 0</doc> + <doc>Array-of-Structures Address 0</doc> <bitfield name="VTX_AOS_ADDR0" high="31" low="2"><doc>Base Address of the Array of Structures.</doc></bitfield> </reg32> </stripe> <stripe offset="0x20C4" stride="0x0000" length="1415"> <reg32 name="VAP_VTX_AOS_ATTR" access="rw" offset="0x0000"> - <doc>Array-of-Structures Attributes 0 & 1</doc> + <doc>Array-of-Structures Attributes 0 & 1</doc> <bitfield name="VTX_AOS_COUNT0" high="6" low="0"><doc>Number of dwords in this structure.</doc></bitfield> <bitfield name="VTX_AOS_STRIDE0" high="14" low="8"><doc>Number of dwords from one array element to the next.</doc></bitfield> <bitfield name="VTX_AOS_COUNT1" high="22" low="16"><doc>Number of dwords in this structure.</doc></bitfield> @@ -1403,7 +1409,9 @@ </bitfield> <bitfield name="DEPTHMICROTILE" high="18" low="17"> <doc>Specifies whether Z buffer is micro-tiled. micro-tiles is 32 bytes</doc> - <use-enum ref="ENUM92" /> + <value value="0" name="32_BYTE_CACHE_LINE_IS_LINEAR"><doc>32 byte cache line is linear</doc></value> + <value value="1" name="32_BYTE_CACHE_LINE_IS_TILED"><doc>32 byte cache line is tiled</doc></value> + <value value="2" name="32_BYTE_CACHE_LINE_IS_TILED_SQUARE"><doc>32 byte cache line is tiled square (only applies to 16-bit pixels)</doc></value> </bitfield> <bitfield name="DEPTHENDIAN" high="20" low="19"> <doc>Specifies endian control for the Z buffer.</doc> @@ -1451,9 +1459,7 @@ <bitfield name="ZPASS_ADDR" high="31" low="2"><doc>Writing this location with a DWORD address causes the value in ZB_ZPASS_DATA to be written to main memory at the location pointed to by this address. NOTE: R300 has 2 pixel pipes. Broadcasting this address causes both pipes to write their ZPASS value to the same address. There is no guarantee which pipe will write last. So when writing to this register, the GA needs to be programmed to send the write command to pipe 0. Then a different address needs to be written to pipe 1. Then both pipes should be enabled for further register writes.</doc></bitfield> </reg32> <reg32 name="ZB_ZTOP" access="rw" offset="0x4F14"> - <doc></doc> <bitfield name="ZTOP" high="0" low="0"> - <doc></doc> <value value="0" name="Z_IS_AT_THE_BOTTOM_OF_THE_PIPE"><doc>Z is at the bottom of the pipe, after the fog unit.</doc></value> <value value="1" name="Z_IS_AT_THE_TOP_OF_THE_PIPE"><doc>Z is at the top of the pipe, after the scan unit.</doc></value> </bitfield> @@ -1491,10 +1497,10 @@ <value value="0" name="DISABLE"><doc>Disable</doc></value> <value value="1" name="DISCARD_PIXELS_IF_SRC_ALPHA"><doc>Discard pixels if src alpha == 0</doc></value> <value value="2" name="DISCARD_PIXELS_IF_SRC_COLOR"><doc>Discard pixels if src color == 0</doc></value> - <value value="3" name="DISCARD_PIXELS_IF"><doc>Discard pixels if (src alpha == 0) && (src color</doc></value> + <value value="3" name="DISCARD_PIXELS_IF"><doc>Discard pixels if (src alpha == 0) && (src color == 0)</doc></value> <value value="4" name="DISCARD_PIXELS_IF_SRC_ALPHA"><doc>Discard pixels if src alpha == 1</doc></value> <value value="5" name="DISCARD_PIXELS_IF_SRC_COLOR"><doc>Discard pixels if src color == 1</doc></value> - <value value="6" name="DISCARD_PIXELS_IF"><doc>Discard pixels if (src alpha == 1) && (src color</doc></value> + <value value="6" name="DISCARD_PIXELS_IF"><doc>Discard pixels if (src alpha == 1) && (src color == 1)</doc></value> </bitfield> <bitfield name="COMB_FCN" high="14" low="12"> <doc>Combine Function , Allows modification of how the SRCBLEND and DESTBLEND are combined.</doc> @@ -1513,10 +1519,7 @@ <doc>Unpipelined.</doc> <bitfield name="NUM_MULTIWRITES" high="6" low="5"> <doc>A quad is replicated and written to this many buffers.</doc> - <value value="0" name="1_BUFFER"><doc>1 buffer. This is the only mode where the cb</doc></value> - <value value="1" name="2_BUFFERS"><doc>2 buffers</doc></value> - <value value="2" name="3_BUFFERS"><doc>3 buffers</doc></value> - <value value="3" name="4_BUFFERS"><doc>4 buffers</doc></value> + <use-enum ref="ENUM7" /> </bitfield> <bitfield name="CLRCMP_FLIPE_ENABLE" high="7" low="7"> <doc>Enables equivalent of rage128 CMP_EQ_FLIP color compare mode. This is used to ensure 3D data does not get chromakeyed away by logic in the backend.</doc> @@ -1530,7 +1533,7 @@ </reg32> <stripe offset="0x4E38" stride="0x0004" length="4"> <reg32 name="RB3D_COLORPITCH" access="rw" offset="0x0000"> - <doc>Color buffer format and tiling control for all the multibuffers and the pitch of multibuffer 0. Unpipelined. The cache must be empty before any of the registers are changed.</doc> + <doc>Color buffer format and tiling control for all the multibuffers and the pitch of multibuffer 0. Unpipelined. The cache must be empty before any of the registers are changed.</doc> <bitfield name="COLORPITCH" high="13" low="1"><doc>3D destination pitch in multiples of 2-pixels.</doc></bitfield> <bitfield name="COLORTILE" high="16" low="16"> <doc>Denotes whether the 3D destination is in macrotiled format.</doc> @@ -1715,49 +1718,49 @@ </bitfield> <bitfield name="TEX0_SOURCE" high="17" low="16"> <doc>Specifies the source of the texture coordinates for this texture.</doc> - <value value="0" name="REPLICATE_VAP_SOURCE_TEXTURE_COORDINATES_0"><doc>Replicate VAP source texture coordinates 0</doc></value> + <value value="0" name="REPLICATE_VAP_SOURCE_TEXTURE_COORDINATES_0"><doc>Replicate VAP source texture coordinates 0 (S,T,[R,Q]).</doc></value> <value value="1" name="STUFF_WITH_SOURCE_TEXTURE_COORDINATES"><doc>Stuff with source texture coordinates (S,T).</doc></value> <value value="2" name="STUFF_WITH_SOURCE_TEXTURE_COORDINATES"><doc>Stuff with source texture coordinates (S,T,R).</doc></value> </bitfield> <bitfield name="TEX1_SOURCE" high="19" low="18"> <doc>Specifies the source of the texture coordinates for this texture.</doc> - <value value="0" name="REPLICATE_VAP_SOURCE_TEXTURE_COORDINATES_1"><doc>Replicate VAP source texture coordinates 1</doc></value> + <value value="0" name="REPLICATE_VAP_SOURCE_TEXTURE_COORDINATES_1"><doc>Replicate VAP source texture coordinates 1 (S,T,[R,Q]).</doc></value> <value value="1" name="STUFF_WITH_SOURCE_TEXTURE_COORDINATES"><doc>Stuff with source texture coordinates (S,T).</doc></value> <value value="2" name="STUFF_WITH_SOURCE_TEXTURE_COORDINATES"><doc>Stuff with source texture coordinates (S,T,R).</doc></value> </bitfield> <bitfield name="TEX2_SOURCE" high="21" low="20"> <doc>Specifies the source of the texture coordinates for this texture.</doc> - <value value="0" name="REPLICATE_VAP_SOURCE_TEXTURE_COORDINATES_2"><doc>Replicate VAP source texture coordinates 2</doc></value> + <value value="0" name="REPLICATE_VAP_SOURCE_TEXTURE_COORDINATES_2"><doc>Replicate VAP source texture coordinates 2 (S,T,[R,Q]).</doc></value> <value value="1" name="STUFF_WITH_SOURCE_TEXTURE_COORDINATES"><doc>Stuff with source texture coordinates (S,T).</doc></value> <value value="2" name="STUFF_WITH_SOURCE_TEXTURE_COORDINATES"><doc>Stuff with source texture coordinates (S,T,R).</doc></value> </bitfield> <bitfield name="TEX3_SOURCE" high="23" low="22"> <doc>Specifies the source of the texture coordinates for this texture.</doc> - <value value="0" name="REPLICATE_VAP_SOURCE_TEXTURE_COORDINATES_3"><doc>Replicate VAP source texture coordinates 3</doc></value> + <value value="0" name="REPLICATE_VAP_SOURCE_TEXTURE_COORDINATES_3"><doc>Replicate VAP source texture coordinates 3 (S,T,[R,Q]).</doc></value> <value value="1" name="STUFF_WITH_SOURCE_TEXTURE_COORDINATES"><doc>Stuff with source texture coordinates (S,T).</doc></value> <value value="2" name="STUFF_WITH_SOURCE_TEXTURE_COORDINATES"><doc>Stuff with source texture coordinates (S,T,R).</doc></value> </bitfield> <bitfield name="TEX4_SOURCE" high="25" low="24"> <doc>Specifies the source of the texture coordinates for this texture.</doc> - <value value="0" name="REPLICATE_VAP_SOURCE_TEXTURE_COORDINATES_4"><doc>Replicate VAP source texture coordinates 4</doc></value> + <value value="0" name="REPLICATE_VAP_SOURCE_TEXTURE_COORDINATES_4"><doc>Replicate VAP source texture coordinates 4 (S,T,[R,Q]).</doc></value> <value value="1" name="STUFF_WITH_SOURCE_TEXTURE_COORDINATES"><doc>Stuff with source texture coordinates (S,T).</doc></value> <value value="2" name="STUFF_WITH_SOURCE_TEXTURE_COORDINATES"><doc>Stuff with source texture coordinates (S,T,R).</doc></value> </bitfield> <bitfield name="TEX5_SOURCE" high="27" low="26"> <doc>Specifies the source of the texture coordinates for this texture.</doc> - <value value="0" name="REPLICATE_VAP_SOURCE_TEXTURE_COORDINATES_5"><doc>Replicate VAP source texture coordinates 5</doc></value> + <value value="0" name="REPLICATE_VAP_SOURCE_TEXTURE_COORDINATES_5"><doc>Replicate VAP source texture coordinates 5 (S,T,[R,Q]).</doc></value> <value value="1" name="STUFF_WITH_SOURCE_TEXTURE_COORDINATES"><doc>Stuff with source texture coordinates (S,T).</doc></value> <value value="2" name="STUFF_WITH_SOURCE_TEXTURE_COORDINATES"><doc>Stuff with source texture coordinates (S,T,R).</doc></value> </bitfield> <bitfield name="TEX6_SOURCE" high="29" low="28"> <doc>Specifies the source of the texture coordinates for this texture.</doc> - <value value="0" name="REPLICATE_VAP_SOURCE_TEXTURE_COORDINATES_6"><doc>Replicate VAP source texture coordinates 6</doc></value> + <value value="0" name="REPLICATE_VAP_SOURCE_TEXTURE_COORDINATES_6"><doc>Replicate VAP source texture coordinates 6 (S,T,[R,Q]).</doc></value> <value value="1" name="STUFF_WITH_SOURCE_TEXTURE_COORDINATES"><doc>Stuff with source texture coordinates (S,T).</doc></value> <value value="2" name="STUFF_WITH_SOURCE_TEXTURE_COORDINATES"><doc>Stuff with source texture coordinates (S,T,R).</doc></value> </bitfield> <bitfield name="TEX7_SOURCE" high="31" low="30"> <doc>Specifies the source of the texture coordinates for this texture.</doc> - <value value="0" name="REPLICATE_VAP_SOURCE_TEXTURE_COORDINATES_7"><doc>Replicate VAP source texture coordinates 7</doc></value> + <value value="0" name="REPLICATE_VAP_SOURCE_TEXTURE_COORDINATES_7"><doc>Replicate VAP source texture coordinates 7 (S,T,[R,Q]).</doc></value> <value value="1" name="STUFF_WITH_SOURCE_TEXTURE_COORDINATES"><doc>Stuff with source texture coordinates (S,T).</doc></value> <value value="2" name="STUFF_WITH_SOURCE_TEXTURE_COORDINATES"><doc>Stuff with source texture coordinates (S,T,R).</doc></value> </bitfield> @@ -1884,7 +1887,7 @@ </reg32> <stripe offset="0x4330" stride="0x0004" length="16"> <reg32 name="RS_INST" access="rw" offset="0x0000"> - <doc>This table specifies what happens during each rasterizer instruction</doc> + <doc>This table specifies what happens during each rasterizer instruction</doc> <bitfield name="TEX_ID" high="2" low="0"><doc>Specifies the index (into the RS_IP table) of the texture address output during this rasterizer instruction</doc></bitfield> <bitfield name="TEX_CN" high="5" low="3"> <doc>Write enable for texture address</doc> @@ -1923,7 +1926,7 @@ </reg32> <stripe offset="0x4310" stride="0x0000" length="8"> <reg32 name="RS_IP" access="rw" offset="0x0000"> - <doc>This table specifies the source location and format for up to 8 texture addresses (i[0]:i[7]) and four colors (c[0]:c[3])</doc> + <doc>This table specifies the source location and format for up to 8 texture addresses (i[0]:i[7]) and four colors (c[0]:c[3])</doc> <bitfield name="TEX_PTR" high="5" low="0"><doc>Specifies the relative rasterizer input packet location of texture address (i[i]).</doc></bitfield> <bitfield name="COL_PTR" high="8" low="6"><doc>Specifies the relative rasterizer input packet location of the color (c[i]).</doc></bitfield> <bitfield name="COL_FMT" high="12" low="9"> @@ -1985,143 +1988,47 @@ </reg32> <reg32 name="SU_TEX_WRAP" access="rw" offset="0x42A0"> <doc>Enables for Cylindrical Wrapping</doc> - <bitfield name="T0C0" high="0" low="0"> - <doc></doc> - <use-enum ref="ENUM5" /> - </bitfield> - <bitfield name="T0C1" high="1" low="1"> - <doc></doc> - <use-enum ref="ENUM5" /> - </bitfield> - <bitfield name="T0C2" high="2" low="2"> - <doc></doc> - <use-enum ref="ENUM5" /> - </bitfield> - <bitfield name="T0C3" high="3" low="3"> - <doc></doc> - <use-enum ref="ENUM5" /> - </bitfield> - <bitfield name="T1C0" high="4" low="4"> - <doc></doc> - <use-enum ref="ENUM5" /> - </bitfield> - <bitfield name="T1C1" high="5" low="5"> - <doc></doc> - <use-enum ref="ENUM5" /> - </bitfield> - <bitfield name="T1C2" high="6" low="6"> - <doc></doc> - <use-enum ref="ENUM5" /> - </bitfield> - <bitfield name="T1C3" high="7" low="7"> - <doc></doc> - <use-enum ref="ENUM5" /> - </bitfield> - <bitfield name="T2C0" high="8" low="8"> - <doc></doc> - <use-enum ref="ENUM5" /> - </bitfield> - <bitfield name="T2C1" high="9" low="9"> - <doc></doc> - <use-enum ref="ENUM5" /> - </bitfield> - <bitfield name="T2C2" high="10" low="10"> - <doc></doc> - <use-enum ref="ENUM5" /> - </bitfield> - <bitfield name="T2C3" high="11" low="11"> - <doc></doc> - <use-enum ref="ENUM5" /> - </bitfield> - <bitfield name="T3C0" high="12" low="12"> - <doc></doc> - <use-enum ref="ENUM5" /> - </bitfield> - <bitfield name="T3C1" high="13" low="13"> - <doc></doc> - <use-enum ref="ENUM5" /> - </bitfield> - <bitfield name="T3C2" high="14" low="14"> - <doc></doc> - <use-enum ref="ENUM5" /> - </bitfield> - <bitfield name="T3C3" high="15" low="15"> - <doc></doc> - <use-enum ref="ENUM5" /> - </bitfield> - <bitfield name="T4C0" high="16" low="16"> - <doc></doc> - <use-enum ref="ENUM5" /> - </bitfield> - <bitfield name="T4C1" high="17" low="17"> - <doc></doc> - <use-enum ref="ENUM5" /> - </bitfield> - <bitfield name="T4C2" high="18" low="18"> - <doc></doc> - <use-enum ref="ENUM5" /> - </bitfield> - <bitfield name="T4C3" high="19" low="19"> - <doc></doc> - <use-enum ref="ENUM5" /> - </bitfield> - <bitfield name="T5C0" high="20" low="20"> - <doc></doc> - <use-enum ref="ENUM5" /> - </bitfield> - <bitfield name="T5C1" high="21" low="21"> - <doc></doc> - <use-enum ref="ENUM5" /> - </bitfield> - <bitfield name="T5C2" high="22" low="22"> - <doc></doc> - <use-enum ref="ENUM5" /> - </bitfield> - <bitfield name="T5C3" high="23" low="23"> - <doc></doc> - <use-enum ref="ENUM5" /> - </bitfield> - <bitfield name="T6C0" high="24" low="24"> - <doc></doc> - <use-enum ref="ENUM5" /> - </bitfield> - <bitfield name="T6C1" high="25" low="25"> - <doc></doc> - <use-enum ref="ENUM5" /> - </bitfield> - <bitfield name="T6C2" high="26" low="26"> - <doc></doc> - <use-enum ref="ENUM5" /> - </bitfield> - <bitfield name="T6C3" high="27" low="27"> - <doc></doc> - <use-enum ref="ENUM5" /> - </bitfield> - <bitfield name="T7C0" high="28" low="28"> - <doc></doc> - <use-enum ref="ENUM5" /> - </bitfield> - <bitfield name="T7C1" high="29" low="29"> - <doc></doc> - <use-enum ref="ENUM5" /> - </bitfield> - <bitfield name="T7C2" high="30" low="30"> - <doc></doc> - <use-enum ref="ENUM5" /> - </bitfield> - <bitfield name="T7C3" high="31" low="31"> - <doc></doc> - <use-enum ref="ENUM5" /> - </bitfield> + <bitfield name="T0C0" high="0" low="0"><use-enum ref="ENUM5" /></bitfield> + <bitfield name="T0C1" high="1" low="1"><use-enum ref="ENUM5" /></bitfield> + <bitfield name="T0C2" high="2" low="2"><use-enum ref="ENUM5" /></bitfield> + <bitfield name="T0C3" high="3" low="3"><use-enum ref="ENUM5" /></bitfield> + <bitfield name="T1C0" high="4" low="4"><use-enum ref="ENUM5" /></bitfield> + <bitfield name="T1C1" high="5" low="5"><use-enum ref="ENUM5" /></bitfield> + <bitfield name="T1C2" high="6" low="6"><use-enum ref="ENUM5" /></bitfield> + <bitfield name="T1C3" high="7" low="7"><use-enum ref="ENUM5" /></bitfield> + <bitfield name="T2C0" high="8" low="8"><use-enum ref="ENUM5" /></bitfield> + <bitfield name="T2C1" high="9" low="9"><use-enum ref="ENUM5" /></bitfield> + <bitfield name="T2C2" high="10" low="10"><use-enum ref="ENUM5" /></bitfield> + <bitfield name="T2C3" high="11" low="11"><use-enum ref="ENUM5" /></bitfield> + <bitfield name="T3C0" high="12" low="12"><use-enum ref="ENUM5" /></bitfield> + <bitfield name="T3C1" high="13" low="13"><use-enum ref="ENUM5" /></bitfield> + <bitfield name="T3C2" high="14" low="14"><use-enum ref="ENUM5" /></bitfield> + <bitfield name="T3C3" high="15" low="15"><use-enum ref="ENUM5" /></bitfield> + <bitfield name="T4C0" high="16" low="16"><use-enum ref="ENUM5" /></bitfield> + <bitfield name="T4C1" high="17" low="17"><use-enum ref="ENUM5" /></bitfield> + <bitfield name="T4C2" high="18" low="18"><use-enum ref="ENUM5" /></bitfield> + <bitfield name="T4C3" high="19" low="19"><use-enum ref="ENUM5" /></bitfield> + <bitfield name="T5C0" high="20" low="20"><use-enum ref="ENUM5" /></bitfield> + <bitfield name="T5C1" high="21" low="21"><use-enum ref="ENUM5" /></bitfield> + <bitfield name="T5C2" high="22" low="22"><use-enum ref="ENUM5" /></bitfield> + <bitfield name="T5C3" high="23" low="23"><use-enum ref="ENUM5" /></bitfield> + <bitfield name="T6C0" high="24" low="24"><use-enum ref="ENUM5" /></bitfield> + <bitfield name="T6C1" high="25" low="25"><use-enum ref="ENUM5" /></bitfield> + <bitfield name="T6C2" high="26" low="26"><use-enum ref="ENUM5" /></bitfield> + <bitfield name="T6C3" high="27" low="27"><use-enum ref="ENUM5" /></bitfield> + <bitfield name="T7C0" high="28" low="28"><use-enum ref="ENUM5" /></bitfield> + <bitfield name="T7C1" high="29" low="29"><use-enum ref="ENUM5" /></bitfield> + <bitfield name="T7C2" high="30" low="30"><use-enum ref="ENUM5" /></bitfield> + <bitfield name="T7C3" high="31" low="31"><use-enum ref="ENUM5" /></bitfield> </reg32> <stripe offset="0x45C0" stride="0x0004" length="16"> <reg32 name="TX_BORDER_COLOR" access="rw" offset="0x0000"> - <doc>Border Color for Map 0. Color used for borders. Format is the same as the texture being bordered.</doc> + <doc>Border Color for Map 0. Color used for borders. Format is the same as the texture being bordered.</doc> </reg32> </stripe> <stripe offset="0x4580" stride="0x0004" length="16"> <reg32 name="TX_CHROMA_KEY" access="rw" offset="0x0000"> - <doc>Texture Chroma Key for Map 0. Color used for chroma key compare. Format is the same as the texture being keyed.</doc> + <doc>Texture Chroma Key for Map 0. Color used for chroma key compare. Format is the same as the texture being keyed.</doc> </reg32> </stripe> <reg32 name="TX_ENABLE" access="rw" offset="0x4104"> @@ -2193,7 +2100,7 @@ </reg32> <stripe offset="0x4400" stride="0x0004" length="16"> <reg32 name="TX_FILTER0" access="rw" offset="0x0000"> - <doc>Texture Filter State for Map 0</doc> + <doc>Texture Filter State for Map 0</doc> <bitfield name="CLAMP_S" high="2" low="0"> <doc>Clamp mode for first texture coordinate</doc> <use-enum ref="ENUM69" /> @@ -2228,7 +2135,7 @@ </stripe> <stripe offset="0x4440" stride="0x0004" length="16"> <reg32 name="TX_FILTER1" access="rw" offset="0x0000"> - <doc>Texture Filter State for Map 0</doc> + <doc>Texture Filter State for Map 0</doc> <bitfield name="CHROMA_KEY_MODE" high="1" low="0"> <doc>Chroma Key Mode</doc> <use-enum ref="ENUM73" /> @@ -2246,7 +2153,7 @@ </stripe> <stripe offset="0x4480" stride="0x0004" length="16"> <reg32 name="TX_FORMAT0" access="rw" offset="0x0000"> - <doc>Texture Format State for Map 0</doc> + <doc>Texture Format State for Map 0</doc> <bitfield name="TXWIDTH" high="10" low="0"><doc>Image width - 1. The largest image is 2048 texels. When wrapping or mirroring, must be a power of 2. When mipmapping, must be a power of 2 or padded to a power of 2 in memory. Can always be non-square, except for cube maps which must be square.</doc></bitfield> <bitfield name="TXHEIGHT" high="21" low="11"><doc>Image height - 1. The largest image is 2048 texels. When wrapping or mirroring, must be a power of 2. When mipmapping, must be a power of 2 or padded to a power of 2 in memory. Can always be non-square, except for cube maps which must be square.</doc></bitfield> <bitfield name="TXDEPTH" high="25" low="22"><doc>LOG2(depth) of volume texture</doc></bitfield> @@ -2263,7 +2170,7 @@ </stripe> <stripe offset="0x44C0" stride="0x0004" length="16"> <reg32 name="TX_FORMAT1" access="rw" offset="0x0000"> - <doc>Texture Format State for Map 0</doc> + <doc>Texture Format State for Map 0</doc> <bitfield name="TXFORMAT" high="4" low="0"> <doc>Texture Format. Components are numbered right to left. Parenthesis indicate typical uses of each format.</doc> <value value="0" name="TX_FMT_8"><doc>TX_FMT_8</doc></value> @@ -2297,30 +2204,30 @@ </bitfield> <bitfield name="SIGNED_COMP0" high="5" low="5"> <doc>Component0 filter should interpret texel data as signed or unsigned. (Ignored for Y/YUV formats.)</doc> - <value value="0" name="COMPONENT0_FILTER_SHOULD_INTERPRET_TEXEL_DATA_AS"><doc>Component0 filter should interpret texel data as</doc></value> - <value value="1" name="COMPONENT0_FILTER_SHOULD_INTERPRET_TEXEL_DATA_AS"><doc>Component0 filter should interpret texel data as</doc></value> + <value value="0" name="COMPONENT0_FILTER_SHOULD_INTERPRET_TEXEL_DATA_AS_UNSIGNED"><doc>Component0 filter should interpret texel data as unsigned</doc></value> + <value value="1" name="COMPONENT0_FILTER_SHOULD_INTERPRET_TEXEL_DATA_AS_SIGNED"><doc>Component0 filter should interpret texel data as signed</doc></value> </bitfield> <bitfield name="SIGNED_COMP1" high="6" low="6"> <doc>Component1 filter should interpret texel data as signed or unsigned. (Ignored for Y/YUV formats.)</doc> - <value value="0" name="COMPONENT1_FILTER_SHOULD_INTERPRET_TEXEL_DATA_AS"><doc>Component1 filter should interpret texel data as</doc></value> - <value value="1" name="COMPONENT1_FILTER_SHOULD_INTERPRET_TEXEL_DATA_AS"><doc>Component1 filter should interpret texel data as</doc></value> + <value value="0" name="COMPONENT1_FILTER_SHOULD_INTERPRET_TEXEL_DATA_AS_UNSIGNED"><doc>Component1 filter should interpret texel data as unsigned</doc></value> + <value value="1" name="COMPONENT1_FILTER_SHOULD_INTERPRET_TEXEL_DATA_AS_SIGNED"><doc>Component1 filter should interpret texel data as signed</doc></value> </bitfield> <bitfield name="SIGNED_COMP2" high="7" low="7"> <doc>Component2 filter should interpret texel data as signed or unsigned. (Ignored for Y/YUV formats.)</doc> - <value value="0" name="COMPONENT2_FILTER_SHOULD_INTERPRET_TEXEL_DATA_AS"><doc>Component2 filter should interpret texel data as</doc></value> - <value value="1" name="COMPONENT2_FILTER_SHOULD_INTERPRET_TEXEL_DATA_AS"><doc>Component2 filter should interpret texel data as</doc></value> + <value value="0" name="COMPONENT2_FILTER_SHOULD_INTERPRET_TEXEL_DATA_AS_UNSIGNED"><doc>Component2 filter should interpret texel data as unsigned</doc></value> + <value value="1" name="COMPONENT2_FILTER_SHOULD_INTERPRET_TEXEL_DATA_AS_SIGNED"><doc>Component2 filter should interpret texel data as signed</doc></value> </bitfield> <bitfield name="SIGNED_COMP3" high="8" low="8"> <doc>Component3 filter should interpret texel data as signed or unsigned. (Ignored for Y/YUV formats.)</doc> - <value value="0" name="COMPONENT3_FILTER_SHOULD_INTERPRET_TEXEL_DATA_AS"><doc>Component3 filter should interpret texel data as</doc></value> - <value value="1" name="COMPONENT3_FILTER_SHOULD_INTERPRET_TEXEL_DATA_AS"><doc>Component3 filter should interpret texel data as</doc></value> + <value value="0" name="COMPONENT3_FILTER_SHOULD_INTERPRET_TEXEL_DATA_AS_UNSIGNED"><doc>Component3 filter should interpret texel data as unsigned</doc></value> + <value value="1" name="COMPONENT3_FILTER_SHOULD_INTERPRET_TEXEL_DATA_AS_SIGNED"><doc>Component3 filter should interpret texel data as signed</doc></value> </bitfield> <bitfield name="SEL_ALPHA" high="11" low="9"> <doc>Specifies swizzling for alpha channel at the input of the pixel shader. (Ignored for Y/YUV formats.)</doc> - <value value="0" name="SELECT_TEXTURE_COMPONENT0_FOR_THE_ALPHA"><doc>Select Texture Component0 for the Alpha</doc></value> - <value value="1" name="SELECT_TEXTURE_COMPONENT1_FOR_THE_ALPHA"><doc>Select Texture Component1 for the Alpha</doc></value> - <value value="2" name="SELECT_TEXTURE_COMPONENT2_FOR_THE_ALPHA"><doc>Select Texture Component2 for the Alpha</doc></value> - <value value="3" name="SELECT_TEXTURE_COMPONENT3_FOR_THE_ALPHA"><doc>Select Texture Component3 for the Alpha</doc></value> + <value value="0" name="SELECT_TEXTURE_COMPONENT0_FOR_THE_ALPHA_CHANNEL"><doc>Select Texture Component0 for the Alpha Channel.</doc></value> + <value value="1" name="SELECT_TEXTURE_COMPONENT1_FOR_THE_ALPHA_CHANNEL"><doc>Select Texture Component1 for the Alpha Channel.</doc></value> + <value value="2" name="SELECT_TEXTURE_COMPONENT2_FOR_THE_ALPHA_CHANNEL"><doc>Select Texture Component2 for the Alpha Channel.</doc></value> + <value value="3" name="SELECT_TEXTURE_COMPONENT3_FOR_THE_ALPHA_CHANNEL"><doc>Select Texture Component3 for the Alpha Channel.</doc></value> <value value="4" name="SELECT_THE_VALUE_0_FOR_THE_ALPHA_CHANNEL"><doc>Select the value 0 for the Alpha Channel.</doc></value> <value value="5" name="SELECT_THE_VALUE_1_FOR_THE_ALPHA_CHANNEL"><doc>Select the value 1 for the Alpha Channel.</doc></value> </bitfield> @@ -2335,19 +2242,19 @@ </bitfield> <bitfield name="SEL_GREEN" high="17" low="15"> <doc>Specifies swizzling for green channel at the input of the pixel shader. (Ignored for Y/YUV formats.)</doc> - <value value="0" name="SELECT_TEXTURE_COMPONENT0_FOR_THE_GREEN"><doc>Select Texture Component0 for the Green</doc></value> - <value value="1" name="SELECT_TEXTURE_COMPONENT1_FOR_THE_GREEN"><doc>Select Texture Component1 for the Green</doc></value> - <value value="2" name="SELECT_TEXTURE_COMPONENT2_FOR_THE_GREEN"><doc>Select Texture Component2 for the Green</doc></value> - <value value="3" name="SELECT_TEXTURE_COMPONENT3_FOR_THE_GREEN"><doc>Select Texture Component3 for the Green</doc></value> + <value value="0" name="SELECT_TEXTURE_COMPONENT0_FOR_THE_GREEN_CHANNEL"><doc>Select Texture Component0 for the Green Channel.</doc></value> + <value value="1" name="SELECT_TEXTURE_COMPONENT1_FOR_THE_GREEN_CHANNEL"><doc>Select Texture Component1 for the Green Channel.</doc></value> + <value value="2" name="SELECT_TEXTURE_COMPONENT2_FOR_THE_GREEN_CHANNEL"><doc>Select Texture Component2 for the Green Channel.</doc></value> + <value value="3" name="SELECT_TEXTURE_COMPONENT3_FOR_THE_GREEN_CHANNEL"><doc>Select Texture Component3 for the Green Channel.</doc></value> <value value="4" name="SELECT_THE_VALUE_0_FOR_THE_GREEN_CHANNEL"><doc>Select the value 0 for the Green Channel.</doc></value> <value value="5" name="SELECT_THE_VALUE_1_FOR_THE_GREEN_CHANNEL"><doc>Select the value 1 for the Green Channel.</doc></value> </bitfield> <bitfield name="SEL_BLUE" high="20" low="18"> <doc>Specifies swizzling for blue channel at the input of the pixel shader. (Ignored for Y/YUV formats.)</doc> - <value value="0" name="SELECT_TEXTURE_COMPONENT0_FOR_THE_BLUE"><doc>Select Texture Component0 for the Blue</doc></value> - <value value="1" name="SELECT_TEXTURE_COMPONENT1_FOR_THE_BLUE"><doc>Select Texture Component1 for the Blue</doc></value> - <value value="2" name="SELECT_TEXTURE_COMPONENT2_FOR_THE_BLUE"><doc>Select Texture Component2 for the Blue</doc></value> - <value value="3" name="SELECT_TEXTURE_COMPONENT3_FOR_THE_BLUE"><doc>Select Texture Component3 for the Blue</doc></value> + <value value="0" name="SELECT_TEXTURE_COMPONENT0_FOR_THE_BLUE_CHANNEL"><doc>Select Texture Component0 for the Blue Channel.</doc></value> + <value value="1" name="SELECT_TEXTURE_COMPONENT1_FOR_THE_BLUE_CHANNEL"><doc>Select Texture Component1 for the Blue Channel.</doc></value> + <value value="2" name="SELECT_TEXTURE_COMPONENT2_FOR_THE_BLUE_CHANNEL"><doc>Select Texture Component2 for the Blue Channel.</doc></value> + <value value="3" name="SELECT_TEXTURE_COMPONENT3_FOR_THE_BLUE_CHANNEL"><doc>Select Texture Component3 for the Blue Channel.</doc></value> <value value="4" name="SELECT_THE_VALUE_0_FOR_THE_BLUE_CHANNEL"><doc>Select the value 0 for the Blue Channel.</doc></value> <value value="5" name="SELECT_THE_VALUE_1_FOR_THE_BLUE_CHANNEL"><doc>Select the value 1 for the Blue Channel.</doc></value> </bitfield> @@ -2357,14 +2264,9 @@ </bitfield> <bitfield name="YUV_TO_RGB" high="23" low="22"> <doc>YUV to RGB conversion mode</doc> - <value value="0" name="DISABLE_YUV_TO_RGB_CONVERSION"><doc>Disable YUV to RGB conversion</doc></value> - <value value="1" name="ENABLE_YUV_TO_RGB_CONVERSION"><doc>Enable YUV to RGB conversion (with clamp)</doc></value> - <value value="2" name="ENABLE_YUV_TO_RGB_CONVERSION"><doc>Enable YUV to RGB conversion (without clamp)</doc></value> - </bitfield> - <bitfield name="SWAP_YUV" high="24" low="24"> - <doc></doc> - <use-enum ref="ENUM5" /> + <use-enum ref="ENUM87" /> </bitfield> + <bitfield name="SWAP_YUV" high="24" low="24"><use-enum ref="ENUM5" /></bitfield> <bitfield name="TEX_COORD_TYPE" high="26" low="25"> <doc>Specifies coordinate type.</doc> <use-enum ref="ENUM88" /> @@ -2377,7 +2279,7 @@ </stripe> <stripe offset="0x4500" stride="0x0004" length="16"> <reg32 name="TX_FORMAT2" access="rw" offset="0x0000"> - <doc>Texture Format State for Map 0</doc> + <doc>Texture Format State for Map 0</doc> <bitfield name="TXPITCH" high="13" low="0"><doc>Used instead of TXWIDTH for image addressing when TXPITCH_EN is asserted. Pitch is given as number of texels minus one. Maximum pitch is 16K texels.</doc></bitfield> </reg32> </stripe> @@ -2386,7 +2288,7 @@ </reg32> <stripe offset="0x4540" stride="0x0004" length="16"> <reg32 name="TX_OFFSET" access="rw" offset="0x0000"> - <doc>Texture Offset State for Map 0</doc> + <doc>Texture Offset State for Map 0</doc> <bitfield name="ENDIAN_SWAP" high="1" low="0"> <doc>Endian Control</doc> <use-enum ref="ENUM90" /> @@ -2404,7 +2306,7 @@ </stripe> <stripe offset="0x47C0" stride="0x0004" length="64"> <reg32 name="US_ALU_ALPHA_ADDR" access="rw" offset="0x0000"> - <doc>This table specifies the Alpha source addresses for up to 64 ALU instruction. The ALU expects 6 source operands - three for color (rgb0, rgb1, rgb2) and three for alpha (a0, a1, a2).</doc> + <doc>This table specifies the Alpha source addresses for up to 64 ALU instruction. The ALU expects 6 source operands - three for color (rgb0, rgb1, rgb2) and three for alpha (a0, a1, a2).</doc> <bitfield name="ADDR0" high="5" low="0"><doc>Specifies the identity of source operands a0, a1, and a2. Values 0 through 31 specify a location within the current pixel stack frame. Values 32 through 63 specify a constant.</doc></bitfield> <bitfield name="ADDR1" high="11" low="6"><doc>Specifies the identity of source operands a0, a1, and a2. Values 0 through 31 specify a location within the current pixel stack frame. Values 32 through 63 specify a constant.</doc></bitfield> <bitfield name="ADDR2" high="17" low="12"><doc>Specifies the identity of source operands a0, a1, and a2. Values 0 through 31 specify a location within the current pixel stack frame. Values 32 through 63 specify a constant.</doc></bitfield> @@ -2433,7 +2335,7 @@ </stripe> <stripe offset="0x49C0" stride="0x0004" length="64"> <reg32 name="US_ALU_ALPHA_INST" access="rw" offset="0x0000"> - <doc>ALU Alpha Instruction</doc> + <doc>ALU Alpha Instruction</doc> <bitfield name="SEL_A" high="4" low="0"> <doc>Specifies the operand and component select for inputs A, B, and C.</doc> <use-enum ref="ENUM97" /> @@ -2488,7 +2390,7 @@ </stripe> <stripe offset="0x46C0" stride="0x0004" length="64"> <reg32 name="US_ALU_RGB_ADDR" access="rw" offset="0x0000"> - <doc>This table specifies the RGB source and destination addresses for up to 64 ALU instructions. The ALU expects 6 source operands - three for color (rgb0, rgb1, rgb2) and three for alpha (a0, a1, a2).</doc> + <doc>This table specifies the RGB source and destination addresses for up to 64 ALU instructions. The ALU expects 6 source operands - three for color (rgb0, rgb1, rgb2) and three for alpha (a0, a1, a2).</doc> <bitfield name="ADDR0" high="5" low="0"><doc>Specifies the identity of source operands rgb0, rgb1, and rgb2. Values 0 through 31 specify a location within the current pixel stack frame. Values 32 through 63 specify a constant.</doc></bitfield> <bitfield name="ADDR1" high="11" low="6"><doc>Specifies the identity of source operands rgb0, rgb1, and rgb2. Values 0 through 31 specify a location within the current pixel stack frame. Values 32 through 63 specify a constant.</doc></bitfield> <bitfield name="ADDR2" high="17" low="12"><doc>Specifies the identity of source operands rgb0, rgb1, and rgb2. Values 0 through 31 specify a location within the current pixel stack frame. Values 32 through 63 specify a constant.</doc></bitfield> @@ -2509,7 +2411,7 @@ </stripe> <stripe offset="0x48C0" stride="0x0004" length="64"> <reg32 name="US_ALU_RGB_INST" access="rw" offset="0x0000"> - <doc>ALU RGB Instruction</doc> + <doc>ALU RGB Instruction</doc> <bitfield name="SEL_A" high="4" low="0"> <doc>Specifies the operand and component select for inputs A, B, and C.</doc> <use-enum ref="ENUM104" /> @@ -2542,14 +2444,14 @@ <doc>Specifies the operand for this instruction.</doc> <value value="0" name="OP_MAD"><doc>OP_MAD: Result = A*B + C</doc></value> <value value="1" name="OP_DP3"><doc>OP_DP3: Result = A.r*B.r + A.g*B.g + A.b*B.b</doc></value> - <value value="2" name="OP_DP4"><doc>OP_DP4: Result = A.r*B.r + A.g*B.g + A.b*B.b</doc></value> + <value value="2" name="OP_DP4"><doc>OP_DP4: Result = A.r*B.r + A.g*B.g + A.b*B.b + A.a*B.a</doc></value> <value value="3" name="OP_D2A"><doc>OP_D2A: Result = A.r*B.r + A.g*B.g + C.b</doc></value> <value value="4" name="OP_MIN"><doc>OP_MIN: Result = min(A,B)</doc></value> <value value="5" name="OP_MAX"><doc>OP_MAX: Result = max(A,B)</doc></value> <value value="7" name="OP_CND"><doc>OP_CND: Result = cnd(A,B,C) = (C>0.5)?A:B</doc></value> <value value="8" name="OP_CMP"><doc>OP_CMP: Result = cmp(A,B,C) = (C>=0.0)?A:B</doc></value> <value value="9" name="OP_FRC"><doc>OP_FRC: Result = frac(A)</doc></value> - <value value="10" name="OP_SOP"><doc>OP_SOP: Result = ex2,ln2,rcp,rsq from Alpha</doc></value> + <value value="10" name="OP_SOP"><doc>OP_SOP: Result = ex2,ln2,rcp,rsq from Alpha ALU</doc></value> </bitfield> <bitfield name="OMOD" high="29" low="27"> <doc>Specifies the output modifier for this instruction.</doc> @@ -2568,7 +2470,7 @@ </stripe> <stripe offset="0x4610" stride="0x0004" length="4"> <reg32 name="US_CODE_ADDR" access="rw" offset="0x0000"> - <doc>Code Address for Indirection Levels 0 to 3</doc> + <doc>Code Address for Indirection Levels 0 to 3</doc> <bitfield name="ALU_START" high="5" low="0"><doc>Specifies the start address of the ALU microcode segment associated with the current indirection level (0:63)</doc></bitfield> <bitfield name="ALU_SIZE" high="11" low="6"><doc>Specifies the size of the ALU microcode segment associated with the current indirection level (1:64)</doc></bitfield> <bitfield name="TEX_START" high="16" low="12"><doc>Specifies the start address of the texture microcode segment associated with the current indirection level (0:31)</doc></bitfield> @@ -2600,7 +2502,7 @@ </reg32> <stripe offset="0x46A4" stride="0x0004" length="4"> <reg32 name="US_OUT_FMT" access="rw" offset="0x0000"> - <doc>Specifies how the shader output is written to the fog unit for each of up to four render targets</doc> + <doc>Specifies how the shader output is written to the fog unit for each of up to four render targets</doc> <bitfield name="OUT_FMT" high="4" low="0"> <doc>Specifies the number and size of components</doc> <use-enum ref="ENUM109" /> @@ -2630,7 +2532,7 @@ </reg32> <stripe offset="0x4620" stride="0x0004" length="32"> <reg32 name="US_TEX_INST" access="rw" offset="0x0000"> - <doc>Texture Instruction</doc> + <doc>Texture Instruction</doc> <bitfield name="SRC_ADDR" high="4" low="0"><doc>Specifies the location (within the shader pixel stack frame) of the texture address for this instruction</doc></bitfield> <bitfield name="DST_ADDR" high="10" low="6"><doc>Specifies the location (within the shader pixel stack frame) of the returned texture data for this instruction</doc></bitfield> <bitfield name="TEX_ID" high="14" low="11"><doc>Specifies the id of the texture map used for this instruction</doc></bitfield> @@ -2639,7 +2541,7 @@ <value value="0" name="NOP"><doc>NOP: Do nothing</doc></value> <value value="1" name="LD"><doc>LD: Do Texture Lookup (S,T,R)</doc></value> <value value="2" name="TEXKILL"><doc>TEXKILL: Kill pixel if any component is < 0</doc></value> - <value value="3" name="PROJ"><doc>PROJ: Do projected texture lookup</doc></value> + <value value="3" name="PROJ"><doc>PROJ: Do projected texture lookup (S/Q,T/Q,R/Q)</doc></value> <value value="4" name="LODBIAS"><doc>LODBIAS: Do texture lookup with lod bias</doc></value> </bitfield> <bitfield name="OMOD" high="18" low="18"><doc>unused</doc></bitfield> @@ -2660,25 +2562,25 @@ </reg32> <stripe offset="0x4C0C" stride="0x0010" length="32"> <reg32 name="US_ALU_CONST_A" access="rw" offset="0x0000"> - <doc>Shader Constant Color 0 Alpha Component</doc> + <doc>Shader Constant Color 0 Alpha Component</doc> <bitfield name="KA" high="23" low="0"><doc>Specifies the alpha component; (S16E7) fixed format.</doc></bitfield> </reg32> </stripe> <stripe offset="0x4C08" stride="0x0010" length="32"> <reg32 name="US_ALU_CONST_B" access="rw" offset="0x0000"> - <doc>Shader Constant Color 0 Blue Component</doc> + <doc>Shader Constant Color 0 Blue Component</doc> <bitfield name="KB" high="23" low="0"><doc>Specifies the blue component; (S16E7) fixed format.</doc></bitfield> </reg32> </stripe> <stripe offset="0x4C04" stride="0x0010" length="32"> <reg32 name="US_ALU_CONST_G" access="rw" offset="0x0000"> - <doc>Shader Constant Color 0 Green Component</doc> + <doc>Shader Constant Color 0 Green Component</doc> <bitfield name="KG" high="23" low="0"><doc>Specifies the green component; (S16E7) fixed format.</doc></bitfield> </reg32> </stripe> <stripe offset="0x4C00" stride="0x0010" length="32"> <reg32 name="US_ALU_CONST_R" access="rw" offset="0x0000"> - <doc>Shader Constant Color 0 Red Component</doc> + <doc>Shader Constant Color 0 Red Component</doc> <bitfield name="KR" high="23" low="0"><doc>Specifies the red component; (S16E7) fixed format.</doc></bitfield> </reg32> </stripe> @@ -2722,7 +2624,7 @@ </reg32> <stripe offset="0x2150" stride="0x0004" length="8"> <reg32 name="VAP_PROG_STREAM_CNTL" access="rw" offset="0x0000"> - <doc>Programmable Stream Control Word 0</doc> + <doc>Programmable Stream Control Word 0</doc> <bitfield name="DATA_TYPE_0" high="3" low="0"><doc>The data type for element 0 0 = FLOAT_1 (Single IEEE Float) 1 = FLOAT_2 (2 IEEE floats) 2 = FLOAT_3 (3 IEEE Floats) 3 = FLOAT_4 (4 IEEE Floats) 4 = BYTE * (1 DWORD w 4 8-bit fixed point values) (X = [7:0], Y = [15:8], Z = [23:16], W = [31:24]) 5 = D3DCOLOR * (Same as BYTE except has X->Z,Z- >X swap for D3D color def) (Z = [7:0], Y = [15:8], X = [23:16], W = [31:24]) 6 = SHORT_2 * (1 DWORD with 2 16-bit fixed point values) (X = [15:0], Y = [31:16], Z = 0.0, W = 1.0) 7 = SHORT_4 * (2 DWORDS with 4(2 per dword) 16- bit fixed point values) (X = DW0 [15:0], Y = DW0 [31:16], Z = DW1 [15:0], W = DW1 [31:16]) 8 = VECTOR_3_TTT * (1 DWORD with 3 10-bit fixed point values) (X = [9:0], Y = [19:10], Z = [29:20], W = 1.0) 9 = VECTOR_3_EET * (1 DWORD with 2 11-bit and 1 10-bit fixed point values) (X = [10:0], Y = [21:11], Z = [31:22], W = 1.0) * These data types use the SIGNED and NORMALIZE flags described below.</doc></bitfield> <bitfield name="SKIP_DWORDS_0" high="7" low="4"><doc>The number of DWORDS to skip (discard) after processing the current element.</doc></bitfield> <bitfield name="DST_VEC_LOC_0" high="12" low="8"><doc>The vector address in the input memory to write this element</doc></bitfield> @@ -2741,7 +2643,7 @@ </stripe> <stripe offset="0x2290" stride="0x0004" length="16"> <reg32 name="VAP_PVS_FLOW_CNTL_LOOP_INDEX" access="rw" offset="0x0000"> - <doc>Programmable Vertex Shader Flow Control Loop Index Register 0</doc> + <doc>Programmable Vertex Shader Flow Control Loop Index Register 0</doc> <bitfield name="PVS_FC_LOOP_INIT_VAL_0" high="7" low="0"><doc>This field stores the automatic loop index register init value. This is an 8-bit unsigned value 0-255. This field is only used if the corresponding control flow instruction is a loop.</doc></bitfield> <bitfield name="PVS_FC_LOOP_STEP_VAL_0" high="15" low="8"><doc>This field stores the automatic loop index register step value. This is an 8-bit 2`s comp signed value -128-127. This field is only used if the corresponding control flow instruction is a loop.</doc></bitfield> </reg32> @@ -2784,44 +2686,16 @@ </reg32> <reg32 name="VAP_VTX_STATE_CNTL" access="rw" offset="0x2180"> <doc>VAP Vertex State Control Register</doc> - <bitfield name="COLOR_0_ASSEMBLY_CNTL" high="1" low="0"> - <doc></doc> - <use-enum ref="ENUM119" /> - </bitfield> - <bitfield name="COLOR_1_ASSEMBLY_CNTL" high="3" low="2"> - <doc></doc> - <use-enum ref="ENUM120" /> - </bitfield> - <bitfield name="COLOR_2_ASSEMBLY_CNTL" high="5" low="4"> - <doc></doc> - <use-enum ref="ENUM121" /> - </bitfield> - <bitfield name="COLOR_3_ASSEMBLY_CNTL" high="7" low="6"> - <doc></doc> - <use-enum ref="ENUM122" /> - </bitfield> - <bitfield name="COLOR_4_ASSEMBLY_CNTL" high="9" low="8"> - <doc></doc> - <use-enum ref="ENUM123" /> - </bitfield> - <bitfield name="COLOR_5_ASSEMBLY_CNTL" high="11" low="10"> - <doc></doc> - <use-enum ref="ENUM124" /> - </bitfield> - <bitfield name="COLOR_6_ASSEMBLY_CNTL" high="13" low="12"> - <doc></doc> - <use-enum ref="ENUM125" /> - </bitfield> - <bitfield name="COLOR_7_ASSEMBLY_CNTL" high="15" low="14"> - <doc></doc> - <use-enum ref="ENUM126" /> - </bitfield> - <bitfield name="UPDATE_USER_COLOR_0_ENA" high="16" low="16"> - <doc></doc> - <use-enum ref="ENUM127" /> - </bitfield> + <bitfield name="COLOR_0_ASSEMBLY_CNTL" high="1" low="0"><use-enum ref="ENUM119" /></bitfield> + <bitfield name="COLOR_1_ASSEMBLY_CNTL" high="3" low="2"><use-enum ref="ENUM120" /></bitfield> + <bitfield name="COLOR_2_ASSEMBLY_CNTL" high="5" low="4"><use-enum ref="ENUM121" /></bitfield> + <bitfield name="COLOR_3_ASSEMBLY_CNTL" high="7" low="6"><use-enum ref="ENUM122" /></bitfield> + <bitfield name="COLOR_4_ASSEMBLY_CNTL" high="9" low="8"><use-enum ref="ENUM123" /></bitfield> + <bitfield name="COLOR_5_ASSEMBLY_CNTL" high="11" low="10"><use-enum ref="ENUM124" /></bitfield> + <bitfield name="COLOR_6_ASSEMBLY_CNTL" high="13" low="12"><use-enum ref="ENUM125" /></bitfield> + <bitfield name="COLOR_7_ASSEMBLY_CNTL" high="15" low="14"><use-enum ref="ENUM126" /></bitfield> + <bitfield name="UPDATE_USER_COLOR_0_ENA" high="16" low="16"><use-enum ref="ENUM127" /></bitfield> <bitfield name="USE_ADDR_IND_TBL" high="18" low="18"> - <doc></doc> <value value="0" name="USE_VERTEX_STATE_ADDRESSES_DIRECTLY_TO_WRITE_TO_VERTEX_STATE_MEMORY"><doc>Use vertex state addresses directly to write to vertex state memory.</doc></value> <value value="1" name="USE_ADDRESS_INDIRECTION_TABLE_TO_WRITE_TO_VERTEX_STATE_MEMORY_FOR_LOWER_64_DWORD_ADDRESSES"><doc>Use Address Indirection table to write to vertex state memory for lower 64 DWORD addresses.</doc></value> </bitfield> @@ -2833,14 +2707,8 @@ <doc>Enables hierarchical Z.</doc> <use-enum ref="ENUM5" /> </bitfield> - <bitfield name="HIZ_MIN" high="1" low="1"> - <doc></doc> - <use-enum ref="ENUM129" /> - </bitfield> - <bitfield name="FAST_FILL" high="2" low="2"> - <doc></doc> - <use-enum ref="ENUM5" /> - </bitfield> + <bitfield name="HIZ_MIN" high="1" low="1"><use-enum ref="ENUM129" /></bitfield> + <bitfield name="FAST_FILL" high="2" low="2"><use-enum ref="ENUM5" /></bitfield> <bitfield name="RD_COMP_ENABLE" high="3" low="3"> <doc>Enables reading of compressed Z data from memory to the cache.</doc> <use-enum ref="ENUM5" /> @@ -2851,8 +2719,7 @@ </bitfield> <bitfield name="ZB_CB_CLEAR" high="5" low="5"> <doc>This bit is set when the Z buffer is used to help the CB in clearing a region. Part of the region is cleared by the color buffer and part will be cleared by the Z buffer. Since the Z buffer does not have any write masks in the cache, full micro-tiles need to be written. If a partial micro-tile is touched , then the un-touched part will be unknowns. The cache will operate in write-allocate mode and quads will be accumulated in the cache and then evicted to main memory. The color value is supplied through the ZB_DEPTHCLEARVALUE register.</doc> - <value value="0" name="Z_UNIT_CACHE_CONTROLLER_DOES_RMW"><doc>Z unit cache controller does RMW</doc></value> - <value value="1" name="Z_UNIT_CACHE_CONTROLLER_DOES_CACHE"><doc>Z unit cache controller does cache-line granular Write only</doc></value> + <use-enum ref="ENUM130" /> </bitfield> <bitfield name="FORCE_COMPRESSED_STENCIL" high="6" low="6"><doc>Enabling this bit will force all the compressed stencil values to be</doc></bitfield> </reg32> @@ -2883,10 +2750,9 @@ <doc>Format of the Data in the Z buffer</doc> <bitfield name="DEPTHFORMAT" high="3" low="0"> <doc>Specifies the format of the Z buffer.</doc> - <use-enum ref="ENUM132" /> + <use-enum ref="ENUM133" /> </bitfield> <bitfield name="INVERT" high="4" low="4"> - <doc></doc> <value value="0" name="IN_13E3_FORMAT"><doc>in 13E3 format , count leading 0`s</doc></value> <value value="1" name="IN_13E3_FORMAT"><doc>in 13E3 format , count leading 1`s.</doc></value> </bitfield> @@ -2918,15 +2784,15 @@ <doc>Z and Stencil Function Control</doc> <bitfield name="ZFUNC" high="2" low="0"> <doc>Specifies the Z function.</doc> - <use-enum ref="ENUM138" /> + <use-enum ref="ENUM139" /> </bitfield> <bitfield name="STENCILFUNC" high="5" low="3"> <doc>Specifies the stencil function.</doc> - <use-enum ref="ENUM139" /> + <use-enum ref="ENUM140" /> </bitfield> <bitfield name="STENCILFAIL" high="8" low="6"> <doc>Specifies the stencil value to be written if the stencil test fails.</doc> - <use-enum ref="ENUM140" /> + <use-enum ref="ENUM141" /> </bitfield> <bitfield name="STENCILZPASS" high="11" low="9"><doc>Same encoding as STENCILFAIL. Specifies the stencil value to be written if the stencil test passes and the Z test passes (or is not enabled).</doc></bitfield> <bitfield name="STENCILZFAIL" high="14" low="12"><doc>Same encoding as STENCILFAIL. Specifies the stencil value to be written if the stencil test passes and the Z test fails.</doc></bitfield> @@ -2982,20 +2848,11 @@ <doc>Alternate Command Stream Queue Control</doc> <bitfield name="INDIRECT2_START" high="6" low="0"><doc>Start location of Indirect Queue #2 in the command cache. This value also sets the size in double octwords of the Indirect Queue #1 cache that will reside in locations INDIRECT1_START to (INDIRECT2_START - 1). The Indirect Queue #2 will reside in locations INDIRECT2_START to 0x5f. The minimum size of the Indirect Queues must be at least twice the MAX_FETCH size as programmed in the CP_RB_CNTL register.</doc></bitfield> <bitfield name="INDIRECT1_START" high="14" low="8"><doc>Start location of Indirect Queue #1 in the command cache. This value is also the size in double octwords of the Primary Queue cache that will reside in locations 0 to (INDIRECT1_START - 1). The minimum size of the Primary Queue cache must be at least twice the MAX_FETCH size as programmed in the CP_RB_CNTL register.</doc></bitfield> - <bitfield name="CSQ_INDIRECT2_MODE" high="26" low="26"> - <doc></doc> - <use-enum ref="ENUM143" /> - </bitfield> + <bitfield name="CSQ_INDIRECT2_MODE" high="26" low="26"><use-enum ref="ENUM144" /></bitfield> <bitfield name="CSQ_INDIRECT2_ENABLE" high="27" low="27"><doc>Enables Indirect Buffer #2. If this bit is set, the CP_CSQ_MODE register overrides the operation of the CSQ_MODE variable in the CP_CSQ_CNTL register.</doc></bitfield> - <bitfield name="CSQ_INDIRECT1_MODE" high="28" low="28"> - <doc></doc> - <use-enum ref="ENUM143" /> - </bitfield> + <bitfield name="CSQ_INDIRECT1_MODE" high="28" low="28"><use-enum ref="ENUM144" /></bitfield> <bitfield name="CSQ_INDIRECT1_ENABLE" high="29" low="29"><doc>Enables Indirect Buffer #1. If this bit is set, the CP_CSQ_MODE register overrides the operation of the CSQ_MODE variable in the CP_CSQ_CNTL register.</doc></bitfield> - <bitfield name="CSQ_PRIMARY_MODE" high="30" low="30"> - <doc></doc> - <use-enum ref="ENUM143" /> - </bitfield> + <bitfield name="CSQ_PRIMARY_MODE" high="30" low="30"><use-enum ref="ENUM144" /></bitfield> <bitfield name="CSQ_PRIMARY_ENABLE" high="31" low="31"><doc>Enables Primary Buffer. If this bit is set, the CP_CSQ_MODE register overrides the operation of the CSQ_MODE variable in the CP_CSQ_CNTL register.</doc></bitfield> </reg32> <reg32 name="CP_CSQ_STAT" access="r" offset="0x07F8"> @@ -3127,46 +2984,16 @@ </reg32> <reg32 name="CP_VP_ADDR_CNTL" access="rw" offset="0x07E8"> <doc>Virtual vs Physical Address Control - Selects whether the address corresponds to a physical or virtual address in memory.</doc> - <bitfield name="SCRATCH_ALT_VP_WR" high="0" low="0"> - <doc></doc> - <use-enum ref="ENUM145" /> - </bitfield> - <bitfield name="SCRATCH_VP_WR" high="1" low="1"> - <doc></doc> - <use-enum ref="ENUM145" /> - </bitfield> - <bitfield name="RPTR_VP_UPDATE" high="2" low="2"> - <doc></doc> - <use-enum ref="ENUM145" /> - </bitfield> - <bitfield name="VIDDMA_VP_WR" high="3" low="3"> - <doc></doc> - <use-enum ref="ENUM145" /> - </bitfield> - <bitfield name="VIDDMA_VP_RD" high="4" low="4"> - <doc></doc> - <use-enum ref="ENUM145" /> - </bitfield> - <bitfield name="GUIDMA_VP_WR" high="5" low="5"> - <doc></doc> - <use-enum ref="ENUM145" /> - </bitfield> - <bitfield name="GUIDMA_VP_RD" high="6" low="6"> - <doc></doc> - <use-enum ref="ENUM145" /> - </bitfield> - <bitfield name="INDR2_VP_FETCH" high="7" low="7"> - <doc></doc> - <use-enum ref="ENUM145" /> - </bitfield> - <bitfield name="INDR1_VP_FETCH" high="8" low="8"> - <doc></doc> - <use-enum ref="ENUM145" /> - </bitfield> - <bitfield name="RING_VP_FETCH" high="9" low="9"> - <doc></doc> - <use-enum ref="ENUM145" /> - </bitfield> + <bitfield name="SCRATCH_ALT_VP_WR" high="0" low="0"><use-enum ref="ENUM146" /></bitfield> + <bitfield name="SCRATCH_VP_WR" high="1" low="1"><use-enum ref="ENUM146" /></bitfield> + <bitfield name="RPTR_VP_UPDATE" high="2" low="2"><use-enum ref="ENUM146" /></bitfield> + <bitfield name="VIDDMA_VP_WR" high="3" low="3"><use-enum ref="ENUM146" /></bitfield> + <bitfield name="VIDDMA_VP_RD" high="4" low="4"><use-enum ref="ENUM146" /></bitfield> + <bitfield name="GUIDMA_VP_WR" high="5" low="5"><use-enum ref="ENUM146" /></bitfield> + <bitfield name="GUIDMA_VP_RD" high="6" low="6"><use-enum ref="ENUM146" /></bitfield> + <bitfield name="INDR2_VP_FETCH" high="7" low="7"><use-enum ref="ENUM146" /></bitfield> + <bitfield name="INDR1_VP_FETCH" high="8" low="8"><use-enum ref="ENUM146" /></bitfield> + <bitfield name="RING_VP_FETCH" high="9" low="9"><use-enum ref="ENUM146" /></bitfield> </reg32> <reg32 name="RB3D_AARESOLVE_CTL" access="rw" offset="0x4E88"> <doc>Resolve Buffer Control. Unpipelined</doc> @@ -3180,9 +3007,8 @@ </bitfield> <bitfield name="AARESOLVE_ALPHA" high="2" low="2"> <doc>Controls whether alpha is averaged in the resolve. 0 => the resolved alpha value is selected from the sample 0 value. 1=> the resolved alpha value is a filtered (average) result of of the samples.</doc> - <value value="1" name=""><doc>> the resolved alpha value is a filtered (average)</doc></value> <value value="0" name="RESOLVED_ALPHA_VALUE_IS_TAKEN_FROM_SAMPLE_0"><doc>Resolved alpha value is taken from sample 0.</doc></value> - <value value="1" name="RESOLVED_ALPHA_VALUE_IS_THE_AVERAGE_OF_THE"><doc>Resolved alpha value is the average of the</doc></value> + <value value="1" name="RESOLVED_ALPHA_VALUE_IS_THE_AVERAGE_OF_THE_SAMPLES"><doc>Resolved alpha value is the average of the samples. The average is not gamma corrected.</doc></value> </bitfield> </reg32> <reg32 name="RB3D_BLENDCNTL" access="rw" offset="0x4E04"> @@ -3202,12 +3028,12 @@ <bitfield name="DISCARD_SRC_PIXELS" high="5" low="3"> <doc>Discard pixels when blending is enabled based on the src color.</doc> <value value="0" name="DISABLE"><doc>Disable</doc></value> - <value value="1" name="DISCARD_PIXELS_IF_SRC_ALPHA"><doc>Discard pixels if src alpha <=</doc></value> - <value value="2" name="DISCARD_PIXELS_IF_SRC_COLOR"><doc>Discard pixels if src color <=</doc></value> - <value value="3" name="DISCARD_PIXELS_IF_SRC_ARGB"><doc>Discard pixels if src argb <=</doc></value> - <value value="4" name="DISCARD_PIXELS_IF_SRC_ALPHA"><doc>Discard pixels if src alpha >=</doc></value> - <value value="5" name="DISCARD_PIXELS_IF_SRC_COLOR"><doc>Discard pixels if src color >=</doc></value> - <value value="6" name="DISCARD_PIXELS_IF_SRC_ARGB"><doc>Discard pixels if src argb >=</doc></value> + <value value="1" name="DISCARD_PIXELS_IF_SRC_ALPHA"><doc>Discard pixels if src alpha <= RB3D_DISCARD_SRC_PIXEL_LTE_THRESHOLD</doc></value> + <value value="2" name="DISCARD_PIXELS_IF_SRC_COLOR"><doc>Discard pixels if src color <= RB3D_DISCARD_SRC_PIXEL_LTE_THRESHOLD</doc></value> + <value value="3" name="DISCARD_PIXELS_IF_SRC_ARGB"><doc>Discard pixels if src argb <= RB3D_DISCARD_SRC_PIXEL_LTE_THRESHOLD</doc></value> + <value value="4" name="DISCARD_PIXELS_IF_SRC_ALPHA"><doc>Discard pixels if src alpha >= RB3D_DISCARD_SRC_PIXEL_GTE_THRESHOLD</doc></value> + <value value="5" name="DISCARD_PIXELS_IF_SRC_COLOR"><doc>Discard pixels if src color >= RB3D_DISCARD_SRC_PIXEL_GTE_THRESHOLD</doc></value> + <value value="6" name="DISCARD_PIXELS_IF_SRC_ARGB"><doc>Discard pixels if src argb >= RB3D_DISCARD_SRC_PIXEL_GTE_THRESHOLD</doc></value> </bitfield> <bitfield name="COMB_FCN" high="14" low="12"> <doc>Combine Function , Allows modification of how the SRCBLEND and DESTBLEND are combined.</doc> @@ -3248,10 +3074,7 @@ <doc>Unpipelined.</doc> <bitfield name="NUM_MULTIWRITES" high="6" low="5"> <doc>A quad is replicated and written to this many buffers.</doc> - <value value="0" name="1_BUFFER"><doc>1 buffer. This is the only mode</doc></value> - <value value="1" name="2_BUFFERS"><doc>2 buffers</doc></value> - <value value="2" name="3_BUFFERS"><doc>3 buffers</doc></value> - <value value="3" name="4_BUFFERS"><doc>4 buffers</doc></value> + <use-enum ref="ENUM7" /> </bitfield> <bitfield name="CLRCMP_FLIPE_ENABLE" high="7" low="7"> <doc>Enables equivalent of rage128 CMP_EQ_FLIP color compare mode. This is used to ensure 3D data does not get chromakeyed away by logic in the backend.</doc> @@ -3282,7 +3105,7 @@ </reg32> <stripe offset="0x4E38" stride="0x0004" length="4"> <reg32 name="RB3D_COLORPITCH" access="rw" offset="0x0000"> - <doc>Color buffer format and tiling control for all the multibuffers and the pitch of multibuffer 0. Unpipelined. The cache must be empty before any of the registers are changed.</doc> + <doc>Color buffer format and tiling control for all the multibuffers and the pitch of multibuffer 0. Unpipelined. The cache must be empty before any of the registers are changed.</doc> <bitfield name="COLORPITCH" high="13" low="1"><doc>3D destination pitch in multiples of 2-pixels.</doc></bitfield> <bitfield name="COLORTILE" high="16" low="16"> <doc>Denotes whether the 3D destination is in macrotiled format.</doc> @@ -3463,8 +3286,8 @@ </bitfield> <bitfield name="FP16_ENABLE" high="28" low="28"> <doc>Enables/Disables FP16 alpha function</doc> - <value value="0" name="DEFAULT_10"><doc>Default 10-bit alpha compare and alpha-to-mask</doc></value> - <value value="1" name="ENABLE_FP16_ALPHA_COMPARE_AND_ALPHA"><doc>Enable FP16 alpha compare and alpha-to-mask</doc></value> + <value value="0" name="DEFAULT_10"><doc>Default 10-bit alpha compare and alpha-to-mask function</doc></value> + <value value="1" name="ENABLE_FP16_ALPHA_COMPARE_AND_ALPHA"><doc>Enable FP16 alpha compare and alpha-to-mask function</doc></value> </bitfield> </reg32> <reg32 name="FG_ALPHA_VALUE" access="rw" offset="0x4BE0"> @@ -3555,12 +3378,11 @@ <bitfield name="REG_READWRITE" high="2" low="2"> <doc>R520+: When set, GA supports simultaneous register reads & writes</doc> <value value="0" name="NO_EFFECT"><doc>No effect.</doc></value> - <value value="1" name="ENABLES_GA_SUPPORT_OF_SIMULTANEOUS_REGISTER"><doc>Enables GA support of simultaneous register</doc></value> + <value value="1" name="ENABLES_GA_SUPPORT_OF_SIMULTANEOUS_REGISTER_READS_AND_WRITES"><doc>Enables GA support of simultaneous register reads and writes.</doc></value> </bitfield> <bitfield name="REG_NOSTALL" high="3" low="3"> - <doc></doc> <value value="0" name="NO_EFFECT"><doc>No effect.</doc></value> - <value value="1" name="ENABLES_GA_SUPPORT_OF_NO"><doc>Enables GA support of no-stall reads for register</doc></value> + <value value="1" name="ENABLES_GA_SUPPORT_OF_NO"><doc>Enables GA support of no-stall reads for register read back.</doc></value> </bitfield> </reg32> <reg32 name="GA_FIFO_CNTL" access="rw" offset="0x4270"> @@ -3677,11 +3499,10 @@ <bitfield name="INDEX" high="8" low="0"><doc>Instruction (TYPE == GA_US_VECTOR_INST) or constant (TYPE == GA_US_VECTOR_CONST) number at which to start loading. The GA will then expect n*6 (instructions) or n*4 (constants) writes to GA_US_VECTOR_DATA. The GA will self-increment until this register is written again. For instructions, the GA expects the dwords in the following order: US_CMN_INST, US_ALU_RGB_ADDR, US_ALU_ALPHA_ADDR, US_ALU_ALPHA, US_RGB_INST, US_ALPHA_INST, US_RGBA_INST. For constants, the GA expects the dwords in RGBA order.</doc></bitfield> <bitfield name="TYPE" high="16" low="16"> <doc>Specifies if the GA should load instructions or constants.</doc> - <value value="0" name="LOAD_INSTRUCTIONS"><doc>Load instructions - INDEX is an instruction</doc></value> + <value value="0" name="LOAD_INSTRUCTIONS"><doc>Load instructions - INDEX is an instruction index</doc></value> <value value="1" name="LOAD_CONSTANTS"><doc>Load constants - INDEX is a constant index</doc></value> </bitfield> <bitfield name="CLAMP" high="17" low="17"> - <doc></doc> <value value="0" name="NO_CLAMPING_OF_DATA"><doc>No clamping of data - Default</doc></value> <value value="1" name="CLAMP_TO"><doc>Clamp to [-1.0,1.0] constant data</doc></value> </bitfield> @@ -3867,7 +3688,7 @@ <bitfield name="PIPE_COUNT" high="3" low="1"> <doc>Specifies the number of active pipes and contexts (up to 4 pipes, 1 ctx). When this field is written, it is automatically reduced by hardware so as not to use more pipes than the number indicated in GB_PIPE_SELECT.MAX_PIPES or the number of pipes left unmasked GB_PIPE_SELECT.BAD_PIPES. The potentially altered value is read back, rather than the original value written by software.</doc> <value value="0" name="RV350"><doc>RV350 (1 pipe, 1 ctx)</doc></value> - <value value="3" name="R300"><doc>R300 (2 pipes, 1 ctx)</doc></value> + <value value="3" name="R300"><doc>R300 (2 pipes, 1 ctx) 06 – R420-3P (3 pipes, 1 ctx) 07 – R420 (4 pipes, 1 ctx)</doc></value> </bitfield> <bitfield name="TILE_SIZE" high="5" low="4"> <doc>Specifies width & height (square), in pixels (only 16, 32 available).</doc> @@ -3919,8 +3740,8 @@ </bitfield> <bitfield name="Z_EXTENDED" high="24" low="24"> <doc>Support for extended setup Z range from [0,1] to [-2,2] with per pixel clamping</doc> - <value value="0" name="USE"><doc>Use (24.1) Z format, with vertex clamp to</doc></value> - <value value="1" name="USE"><doc>Use (S25.1) format, with vertex clamp to [2.0,-</doc></value> + <value value="0" name="USE"><doc>Use (24.1) Z format, with vertex clamp to [1.0,0.0]</doc></value> + <value value="1" name="USE"><doc>Use (S25.1) format, with vertex clamp to [2.0,- 2.0] and per pixel [1.0,0.0]</doc></value> </bitfield> </reg32> <reg32 name="GB_Z_PEQ_CONFIG" access="rw" offset="0x4028"> @@ -3940,7 +3761,7 @@ </reg32> <stripe offset="0x4320" stride="0x0004" length="16"> <reg32 name="RS_INST" access="rw" offset="0x0000"> - <doc>This table specifies what happens during each rasterizer instruction</doc> + <doc>This table specifies what happens during each rasterizer instruction</doc> <bitfield name="TEX_ID" high="3" low="0"><doc>Specifies the index (into the RS_IP table) of the texture address output during this rasterizer instruction</doc></bitfield> <bitfield name="TEX_CN" high="4" low="4"> <doc>Write enable for texture address</doc> @@ -3974,7 +3795,7 @@ </reg32> <stripe offset="0x4074" stride="0x0004" length="16"> <reg32 name="RS_IP" access="rw" offset="0x0000"> - <doc>This table specifies the source location and format for up to 16 texture addresses (i[0]:i[15]) and four colors (c[0]:c[3])</doc> + <doc>This table specifies the source location and format for up to 16 texture addresses (i[0]:i[15]) and four colors (c[0]:c[3])</doc> <bitfield name="TEX_PTR_S" high="5" low="0"><doc>Specifies the relative rasterizer input packet location of each component (S, T, R, and Q) of texture address (i[i]). The values 62 and 63 select constant inputs for the component: 62 selects K0 (0.0), and 63 selects K1 (1.0).</doc></bitfield> <bitfield name="TEX_PTR_T" high="11" low="6"><doc>Specifies the relative rasterizer input packet location of each component (S, T, R, and Q) of texture address (i[i]). The values 62 and 63 select constant inputs for the component: 62 selects K0 (0.0), and 63 selects K1 (1.0).</doc></bitfield> <bitfield name="TEX_PTR_R" high="17" low="12"><doc>Specifies the relative rasterizer input packet location of each component (S, T, R, and Q) of texture address (i[i]). The values 62 and 63 select constant inputs for the component: 62 selects K0 (0.0), and 63 selects K1 (1.0).</doc></bitfield> @@ -3986,8 +3807,8 @@ </bitfield> <bitfield name="OFFSET_EN" high="31" low="31"> <doc>Enable application of the TX_OFFSET in RS_INST_COUNT</doc> - <value value="0" name="DO_NOT_APPLY_THE_TX_OFFSET_IN"><doc>Do not apply the TX_OFFSET in</doc></value> - <value value="1" name="APPLY_THE_TX_OFFSET_SPECIFIED_BY"><doc>Apply the TX_OFFSET specified by</doc></value> + <value value="0" name="DO_NOT_APPLY_THE_TX_OFFSET_IN_RS_INST_COUNT"><doc>Do not apply the TX_OFFSET in RS_INST_COUNT</doc></value> + <value value="1" name="APPLY_THE_TX_OFFSET_SPECIFIED_BY_RS_INST_COUNT"><doc>Apply the TX_OFFSET specified by RS_INST_COUNT</doc></value> </bitfield> </reg32> </stripe> @@ -4196,12 +4017,12 @@ </reg32> <stripe offset="0x45C0" stride="0x0004" length="16"> <reg32 name="TX_BORDER_COLOR" access="rw" offset="0x0000"> - <doc>Border Color. Color used for borders. Format is the same as the texture being bordered.</doc> + <doc>Border Color. Color used for borders. Format is the same as the texture being bordered.</doc> </reg32> </stripe> <stripe offset="0x4580" stride="0x0004" length="16"> <reg32 name="TX_CHROMA_KEY" access="rw" offset="0x0000"> - <doc>Texture Chroma Key. Color used for chroma key compare. Format is the same as the texture being keyed.</doc> + <doc>Texture Chroma Key. Color used for chroma key compare. Format is the same as the texture being keyed.</doc> </reg32> </stripe> <reg32 name="TX_ENABLE" access="rw" offset="0x4104"> @@ -4273,7 +4094,7 @@ </reg32> <stripe offset="0x4400" stride="0x0004" length="16"> <reg32 name="TX_FILTER0" access="rw" offset="0x0000"> - <doc>Texture Filter State</doc> + <doc>Texture Filter State</doc> <bitfield name="CLAMP_S" high="2" low="0"> <doc>Clamp mode for texture coordinates</doc> <use-enum ref="ENUM69" /> @@ -4308,7 +4129,7 @@ </stripe> <stripe offset="0x4440" stride="0x0004" length="16"> <reg32 name="TX_FILTER1" access="rw" offset="0x0000"> - <doc>Texture Filter State</doc> + <doc>Texture Filter State</doc> <bitfield name="CHROMA_KEY_MODE" high="1" low="0"> <doc>Chroma Key Mode</doc> <use-enum ref="ENUM73" /> @@ -4325,9 +4146,9 @@ <bitfield name="TRI_PERF" high="16" low="15"> <doc>Apply slope and bias to trilerp fraction to reduce the number of 2-level fetches for trilinear. Should only be used if MIP_FILTER is LINEAR.</doc> <value value="0" name="BREAKPOINT"><doc>Breakpoint=0/8. lfrac_out = lfrac_in</doc></value> - <value value="1" name="BREAKPOINT"><doc>Breakpoint=1/8. lfrac_out = clamp(4/3*lfrac_in -</doc></value> - <value value="2" name="BREAKPOINT"><doc>Breakpoint=1/4. lfrac_out = clamp(2*lfrac_in -</doc></value> - <value value="3" name="BREAKPOINT"><doc>Breakpoint=3/8. lfrac_out = clamp(4*lfrac_in -</doc></value> + <value value="1" name="BREAKPOINT"><doc>Breakpoint=1/8. lfrac_out = clamp(4/3*lfrac_in - 1/6)</doc></value> + <value value="2" name="BREAKPOINT"><doc>Breakpoint=1/4. lfrac_out = clamp(2*lfrac_in - 1/2)</doc></value> + <value value="3" name="BREAKPOINT"><doc>Breakpoint=3/8. lfrac_out = clamp(4*lfrac_in - 3/2)</doc></value> </bitfield> <bitfield name="Reserved" high="19" low="17"><doc>Set to 0</doc></bitfield> <bitfield name="Reserved" high="20" low="20"><doc>Set to 0</doc></bitfield> @@ -4335,12 +4156,12 @@ <bitfield name="MACRO_SWITCH" high="22" low="22"> <doc>If enabled, addressing switches to macro-linear when image width is <= 8 micro-tiles. If disabled, functionality is same as RV350, switch to macro-linear when image width is < 8 micro-tiles.</doc> <value value="0" name="RV350_MODE"><doc>RV350 mode</doc></value> - <value value="1" name="SWITCH_FROM_MACRO"><doc>Switch from macro-tiled to macro-linear when</doc></value> + <value value="1" name="SWITCH_FROM_MACRO"><doc>Switch from macro-tiled to macro-linear when (width <= 8 micro-tiles)</doc></value> </bitfield> <bitfield name="BORDER_FIX" high="31" low="31"> <doc>To fix issues when using non-square mipmaps, with border_color, and extreme minification.</doc> <value value="0" name="R3XX_R4XX_MODE"><doc>R3xx R4xx mode</doc></value> - <value value="1" name="STOP_RIGHT_SHIFTING_COORD_ONCE_MIP_SIZE_IS_PINNED"><doc>Stop right shifting coord once mip size is pinned</doc></value> + <value value="1" name="STOP_RIGHT_SHIFTING_COORD_ONCE_MIP_SIZE_IS_PINNED_TO_ONE"><doc>Stop right shifting coord once mip size is pinned to one</doc></value> </bitfield> </reg32> </stripe> @@ -4362,7 +4183,7 @@ </reg32> <stripe offset="0x4480" stride="0x0004" length="16"> <reg32 name="TX_FORMAT0" access="rw" offset="0x0000"> - <doc>Texture Format State</doc> + <doc>Texture Format State</doc> <bitfield name="TXWIDTH" high="10" low="0"><doc>Image width - 1. The largest image is 4096 texels. When wrapping or mirroring, must be a power of 2. When mipmapping, must be a power of 2 or padded to a power of 2 in memory. Can always be non-square, except for cube maps which must be square.</doc></bitfield> <bitfield name="TXHEIGHT" high="21" low="11"><doc>Image height - 1. The largest image is 4096 texels. When wrapping or mirroring, must be a power of 2. When mipmapping, must be a power of 2 or padded to a power of 2 in memory. Can always be non-square, except for cube maps which must be square.</doc></bitfield> <bitfield name="TXDEPTH" high="25" low="22"><doc>LOG2(depth) of volume texture</doc></bitfield> @@ -4379,15 +4200,15 @@ </stripe> <stripe offset="0x44C0" stride="0x0004" length="16"> <reg32 name="TX_FORMAT1" access="rw" offset="0x0000"> - <doc>Texture Format State</doc> + <doc>Texture Format State</doc> <bitfield name="TXFORMAT" high="4" low="0"> <doc>Texture Format. Components are numbered right to left. Parenthesis indicate typical uses of each format.</doc> - <value value="0" name="TX_FMT_8_OR_TX_FMT_1"><doc>TX_FMT_8 or TX_FMT_1 (if</doc></value> - <value value="1" name="TX_FMT_16_OR_TX_FMT_1_REVERSE"><doc>TX_FMT_16 or TX_FMT_1_REVERSE (if</doc></value> - <value value="2" name="TX_FMT_4_4_OR_TX_FMT_10"><doc>TX_FMT_4_4 or TX_FMT_10 (if</doc></value> - <value value="3" name="TX_FMT_8_8_OR_TX_FMT_10_10"><doc>TX_FMT_8_8 or TX_FMT_10_10 (if</doc></value> - <value value="4" name="TX_FMT_16_16_OR_TX_FMT_10_10_10_10"><doc>TX_FMT_16_16 or TX_FMT_10_10_10_10 (if</doc></value> - <value value="5" name="TX_FMT_3_3_2_OR_TX_FMT_ATI1N"><doc>TX_FMT_3_3_2 or TX_FMT_ATI1N (if</doc></value> + <value value="0" name="TX_FMT_8_OR_TX_FMT_1"><doc>TX_FMT_8 or TX_FMT_1 (if TX_FORMAT2.TXFORMAT_MSB is set)</doc></value> + <value value="1" name="TX_FMT_16_OR_TX_FMT_1_REVERSE"><doc>TX_FMT_16 or TX_FMT_1_REVERSE (if TX_FORMAT2.TXFORMAT_MSB is set)</doc></value> + <value value="2" name="TX_FMT_4_4_OR_TX_FMT_10"><doc>TX_FMT_4_4 or TX_FMT_10 (if TX_FORMAT2.TXFORMAT_MSB is set)</doc></value> + <value value="3" name="TX_FMT_8_8_OR_TX_FMT_10_10"><doc>TX_FMT_8_8 or TX_FMT_10_10 (if TX_FORMAT2.TXFORMAT_MSB is set)</doc></value> + <value value="4" name="TX_FMT_16_16_OR_TX_FMT_10_10_10_10"><doc>TX_FMT_16_16 or TX_FMT_10_10_10_10 (if TX_FORMAT2.TXFORMAT_MSB is set)</doc></value> + <value value="5" name="TX_FMT_3_3_2_OR_TX_FMT_ATI1N"><doc>TX_FMT_3_3_2 or TX_FMT_ATI1N (if TX_FORMAT2.TXFORMAT_MSB is set)</doc></value> <value value="6" name="TX_FMT_5_6_5"><doc>TX_FMT_5_6_5</doc></value> <value value="7" name="TX_FMT_6_5_5"><doc>TX_FMT_6_5_5</doc></value> <value value="8" name="TX_FMT_11_11_10"><doc>TX_FMT_11_11_10</doc></value> @@ -4450,14 +4271,9 @@ </bitfield> <bitfield name="YUV_TO_RGB" high="23" low="22"> <doc>YUV to RGB conversion mode</doc> - <value value="0" name="DISABLE_YUV_TO_RGB_CONVERSION"><doc>Disable YUV to RGB conversion</doc></value> - <value value="1" name="ENABLE_YUV_TO_RGB_CONVERSION"><doc>Enable YUV to RGB conversion (with clamp)</doc></value> - <value value="2" name="ENABLE_YUV_TO_RGB_CONVERSION"><doc>Enable YUV to RGB conversion (without</doc></value> - </bitfield> - <bitfield name="SWAP_YUV" high="24" low="24"> - <doc></doc> - <use-enum ref="ENUM5" /> + <use-enum ref="ENUM87" /> </bitfield> + <bitfield name="SWAP_YUV" high="24" low="24"><use-enum ref="ENUM5" /></bitfield> <bitfield name="TEX_COORD_TYPE" high="26" low="25"> <doc>Specifies coordinate type.</doc> <use-enum ref="ENUM88" /> @@ -4470,7 +4286,7 @@ </stripe> <stripe offset="0x4500" stride="0x0004" length="16"> <reg32 name="TX_FORMAT2" access="rw" offset="0x0000"> - <doc>Texture Format State</doc> + <doc>Texture Format State</doc> <bitfield name="TXPITCH" high="13" low="0"><doc>Used instead of TXWIDTH for image addressing when TXPITCH_EN is asserted. Pitch is given as number of texels minus one. Maximum pitch is 16K texels.</doc></bitfield> <bitfield name="TXFORMAT_MSB" high="14" low="14"><doc>Specifies the MSB of the texture format to extend the number of formats to 64.</doc></bitfield> <bitfield name="TXWIDTH_11" high="15" low="15"><doc>Specifies bit 11 of TXWIDTH to extend the largest image to 4096 texels.</doc></bitfield> @@ -4494,7 +4310,7 @@ </reg32> <stripe offset="0x4540" stride="0x0004" length="16"> <reg32 name="TX_OFFSET" access="rw" offset="0x0000"> - <doc>Texture Offset State</doc> + <doc>Texture Offset State</doc> <bitfield name="ENDIAN_SWAP" high="1" low="0"> <doc>Endian Control</doc> <use-enum ref="ENUM90" /> @@ -4512,7 +4328,7 @@ </stripe> <stripe offset="0xA800" stride="0x0004" length="512"> <reg32 name="US_ALU_ALPHA_INST" access="rw" offset="0x0000"> - <doc>ALU Alpha Instruction</doc> + <doc>ALU Alpha Instruction</doc> <bitfield name="ALPHA_OP" high="3" low="0"> <doc>Specifies the opcode for this instruction.</doc> <value value="0" name="OP_MAD"><doc>OP_MAD: Result = A*B + C</doc></value> @@ -4520,7 +4336,7 @@ <value value="2" name="OP_MIN"><doc>OP_MIN: Result = min(A,B)</doc></value> <value value="3" name="OP_MAX"><doc>OP_MAX: Result = max(A,B)</doc></value> <value value="5" name="OP_CND"><doc>OP_CND: Result = cnd(A,B,C) = (C>0.5)?A:B</doc></value> - <value value="6" name="OP_CMP"><doc>OP_CMP: Result = cmp(A,B,C) =</doc></value> + <value value="6" name="OP_CMP"><doc>OP_CMP: Result = cmp(A,B,C) = (C>=0.0)?A:B</doc></value> <value value="7" name="OP_FRC"><doc>OP_FRC: Result = A-floor(A)</doc></value> <value value="8" name="OP_EX2"><doc>OP_EX2: Result = 2^^A</doc></value> <value value="9" name="OP_LN2"><doc>OP_LN2: Result = log2(A)</doc></value> @@ -4528,21 +4344,21 @@ <value value="11" name="OP_RSQ"><doc>OP_RSQ: Result = 1/sqrt(A)</doc></value> <value value="12" name="OP_SIN"><doc>OP_SIN: Result = sin(A*2pi)</doc></value> <value value="13" name="OP_COS"><doc>OP_COS: Result = cos(A*2pi)</doc></value> - <value value="14" name="OP_MDH"><doc>OP_MDH: Result = A*B + C; A is always</doc></value> - <value value="15" name="OP_MDV"><doc>OP_MDV: Result = A*B + C; A is always</doc></value> + <value value="14" name="OP_MDH"><doc>OP_MDH: Result = A*B + C; A is always topleft.src0, C is always topright.src0 (source select and swizzles ignored). Input modifiers are respected for all inputs.</doc></value> + <value value="15" name="OP_MDV"><doc>OP_MDV: Result = A*B + C; A is always topleft.src0, C is always bottomleft.src0 (source select and swizzles ignored). Input modifiers are respected for all inputs.</doc></value> </bitfield> <bitfield name="ALPHA_ADDRD" high="10" low="4"><doc>Specifies the address of the pixel stack frame register to which the Alpha result of this instruction is to be written.</doc></bitfield> <bitfield name="ALPHA_ADDRD_REL" high="11" low="11"> <doc>Specifies whether the loop register is added to the value of ALPHA_ADDRD before it is used. This implements relative addressing.</doc> - <use-enum ref="ENUM193" /> + <use-enum ref="ENUM192" /> </bitfield> <bitfield name="ALPHA_SEL_A" high="13" low="12"> <doc>Specifies the operands for Alpha inputs A and B.</doc> - <use-enum ref="ENUM194" /> + <use-enum ref="ENUM193" /> </bitfield> <bitfield name="ALPHA_SWIZ_A" high="16" low="14"> <doc>Specifies the channel sources for Alpha inputs A and B.</doc> - <use-enum ref="ENUM195" /> + <use-enum ref="ENUM194" /> </bitfield> <bitfield name="ALPHA_MOD_A" high="18" low="17"> <doc>Specifies the input modifiers for Alpha inputs A and B.</doc> @@ -4550,11 +4366,11 @@ </bitfield> <bitfield name="ALPHA_SEL_B" high="20" low="19"> <doc>Specifies the operands for Alpha inputs A and B.</doc> - <use-enum ref="ENUM194" /> + <use-enum ref="ENUM193" /> </bitfield> <bitfield name="ALPHA_SWIZ_B" high="23" low="21"> <doc>Specifies the channel sources for Alpha inputs A and B.</doc> - <use-enum ref="ENUM195" /> + <use-enum ref="ENUM194" /> </bitfield> <bitfield name="ALPHA_MOD_B" high="25" low="24"> <doc>Specifies the input modifiers for Alpha inputs A and B.</doc> @@ -4562,11 +4378,11 @@ </bitfield> <bitfield name="OMOD" high="28" low="26"> <doc>Specifies the output modifier for this instruction.</doc> - <use-enum ref="ENUM196" /> + <use-enum ref="ENUM195" /> </bitfield> <bitfield name="TARGET" high="30" low="29"> <doc>This specifies which (cached) frame buffer target to write to. For non-output ALU instructions, this specifies how to compare the results against zero when setting the predicate bits.</doc> - <use-enum ref="ENUM197" /> + <use-enum ref="ENUM196" /> </bitfield> <bitfield name="W_OMASK" high="31" low="31"> <doc>Specifies whether or not to write the Alpha component of the result of this instuction to the depth output fifo.</doc> @@ -4577,33 +4393,33 @@ </stripe> <stripe offset="0x9800" stride="0x0004" length="512"> <reg32 name="US_ALU_ALPHA_ADDR" access="rw" offset="0x0000"> - <doc>This table specifies the Alpha source addresses and pre-subtract operation for up to 512 ALU instruction. The ALU expects 6 source operands - three for color (rgb0, rgb1, rgb2) and three for alpha (a0, a1, a2). The pre-subtract operation creates two more (rgbp and ap).</doc> + <doc>This table specifies the Alpha source addresses and pre-subtract operation for up to 512 ALU instruction. The ALU expects 6 source operands - three for color (rgb0, rgb1, rgb2) and three for alpha (a0, a1, a2). The pre-subtract operation creates two more (rgbp and ap).</doc> <bitfield name="ADDR0" high="7" low="0"><doc>Specifies the identity of source operands a0, a1, and a2. If the const field is set, this number ranges from 0 to 255 and specifies a location within the constant register bank. Otherwise: If the most significant bit is cleared, this field specifies a location within the current pixel stack frame (ranging from 0 to 127). If the most significant bit is set, then the lower 7 bits specify an inline unsigned floating- point constant with 4 bit exponent (bias 7) and 3 bit mantissa, including denormals but excluding infinite/NaN.</doc></bitfield> <bitfield name="ADDR0_CONST" high="8" low="8"> <doc>Specifies whether the associated address is a constant register address or a temporary address / inline constant.</doc> - <use-enum ref="ENUM199" /> + <use-enum ref="ENUM198" /> </bitfield> <bitfield name="ADDR0_REL" high="9" low="9"> <doc>Specifies whether the loop register is added to the value of the associated address before it is used. This implements relative addressing.</doc> - <use-enum ref="ENUM200" /> + <use-enum ref="ENUM199" /> </bitfield> <bitfield name="ADDR1" high="17" low="10"><doc>Specifies the identity of source operands a0, a1, and a2. If the const field is set, this number ranges from 0 to 255 and specifies a location within the constant register bank. Otherwise: If the most significant bit is cleared, this field specifies a location within the current pixel stack frame (ranging from 0 to 127). If the most significant bit is set, then the lower 7 bits specify an inline unsigned floating- point constant with 4 bit exponent (bias 7) and 3 bit mantissa, including denormals but excluding infinite/NaN.</doc></bitfield> <bitfield name="ADDR1_CONST" high="18" low="18"> <doc>Specifies whether the associated address is a constant register address or a temporary address / inline constant.</doc> - <use-enum ref="ENUM199" /> + <use-enum ref="ENUM198" /> </bitfield> <bitfield name="ADDR1_REL" high="19" low="19"> <doc>Specifies whether the loop register is added to the value of the associated address before it is used. This implements relative addressing.</doc> - <use-enum ref="ENUM200" /> + <use-enum ref="ENUM199" /> </bitfield> <bitfield name="ADDR2" high="27" low="20"><doc>Specifies the identity of source operands a0, a1, and a2. If the const field is set, this number ranges from 0 to 255 and specifies a location within the constant register bank. Otherwise: If the most significant bit is cleared, this field specifies a location within the current pixel stack frame (ranging from 0 to 127). If the most significant bit is set, then the lower 7 bits specify an inline unsigned floating- point constant with 4 bit exponent (bias 7) and 3 bit mantissa, including denormals but excluding infinite/NaN.</doc></bitfield> <bitfield name="ADDR2_CONST" high="28" low="28"> <doc>Specifies whether the associated address is a constant register address or a temporary address / inline constant.</doc> - <use-enum ref="ENUM199" /> + <use-enum ref="ENUM198" /> </bitfield> <bitfield name="ADDR2_REL" high="29" low="29"> <doc>Specifies whether the loop register is added to the value of the associated address before it is used. This implements relative addressing.</doc> - <use-enum ref="ENUM200" /> + <use-enum ref="ENUM199" /> </bitfield> <bitfield name="SRCP_OP" high="31" low="30"> <doc>Specifies how the pre-subtract value (SRCP) is computed.</doc> @@ -4613,42 +4429,42 @@ </stripe> <stripe offset="0xB000" stride="0x0004" length="512"> <reg32 name="US_ALU_RGBA_INST" access="rw" offset="0x0000"> - <doc>ALU Shared RGBA Instruction</doc> + <doc>ALU Shared RGBA Instruction</doc> <bitfield name="RGB_OP" high="3" low="0"> <doc>Specifies the opcode for this instruction.</doc> <value value="0" name="OP_MAD"><doc>OP_MAD: Result = A*B + C</doc></value> <value value="1" name="OP_DP3"><doc>OP_DP3: Result = A.r*B.r + A.g*B.g + A.b*B.b</doc></value> - <value value="2" name="OP_DP4"><doc>OP_DP4: Result = A.r*B.r + A.g*B.g + A.b*B.b</doc></value> + <value value="2" name="OP_DP4"><doc>OP_DP4: Result = A.r*B.r + A.g*B.g + A.b*B.b + A.a*B.a</doc></value> <value value="3" name="OP_D2A"><doc>OP_D2A: Result = A.r*B.r + A.g*B.g + C.b</doc></value> <value value="4" name="OP_MIN"><doc>OP_MIN: Result = min(A,B)</doc></value> <value value="5" name="OP_MAX"><doc>OP_MAX: Result = max(A,B)</doc></value> <value value="7" name="OP_CND"><doc>OP_CND: Result = cnd(A,B,C) = (C>0.5)?A:B</doc></value> - <value value="8" name="OP_CMP"><doc>OP_CMP: Result = cmp(A,B,C) =</doc></value> + <value value="8" name="OP_CMP"><doc>OP_CMP: Result = cmp(A,B,C) = (C>=0.0)?A:B</doc></value> <value value="9" name="OP_FRC"><doc>OP_FRC: Result = A-floor(A)</doc></value> - <value value="10" name="OP_SOP"><doc>OP_SOP: Result = ex2,ln2,rcp,rsq,sin,cos from</doc></value> - <value value="11" name="OP_MDH"><doc>OP_MDH: Result = A*B + C; A is always</doc></value> - <value value="12" name="OP_MDV"><doc>OP_MDV: Result = A*B + C; A is always</doc></value> + <value value="10" name="OP_SOP"><doc>OP_SOP: Result = ex2,ln2,rcp,rsq,sin,cos from Alpha ALU</doc></value> + <value value="11" name="OP_MDH"><doc>OP_MDH: Result = A*B + C; A is always topleft.src0, C is always topright.src0 (source select and swizzles ignored). Input modifiers are respected for all inputs.</doc></value> + <value value="12" name="OP_MDV"><doc>OP_MDV: Result = A*B + C; A is always topleft.src0, C is always bottomleft.src0 (source select and swizzles ignored). Input modifiers are respected for all inputs.</doc></value> </bitfield> <bitfield name="RGB_ADDRD" high="10" low="4"><doc>Specifies the address of the pixel stack frame register to which the RGB result of this instruction is to be written.</doc></bitfield> <bitfield name="RGB_ADDRD_REL" high="11" low="11"> <doc>Specifies whether the loop register is added to the value of RGB_ADDRD before it is used. This implements relative addressing.</doc> - <use-enum ref="ENUM193" /> + <use-enum ref="ENUM192" /> </bitfield> <bitfield name="RGB_SEL_C" high="13" low="12"> <doc>Specifies the operands for RGB and Alpha input C.</doc> - <use-enum ref="ENUM194" /> + <use-enum ref="ENUM193" /> </bitfield> <bitfield name="RED_SWIZ_C" high="16" low="14"> <doc>Specifies, per channel, the sources for RGB and Alpha input C.</doc> - <use-enum ref="ENUM195" /> + <use-enum ref="ENUM194" /> </bitfield> <bitfield name="GREEN_SWIZ_C" high="19" low="17"> <doc>Specifies, per channel, the sources for RGB and Alpha input C.</doc> - <use-enum ref="ENUM195" /> + <use-enum ref="ENUM194" /> </bitfield> <bitfield name="BLUE_SWIZ_C" high="22" low="20"> <doc>Specifies, per channel, the sources for RGB and Alpha input C.</doc> - <use-enum ref="ENUM195" /> + <use-enum ref="ENUM194" /> </bitfield> <bitfield name="RGB_MOD_C" high="24" low="23"> <doc>Specifies the input modifiers for RGB and Alpha input C.</doc> @@ -4656,11 +4472,11 @@ </bitfield> <bitfield name="ALPHA_SEL_C" high="26" low="25"> <doc>Specifies the operands for RGB and Alpha input C.</doc> - <use-enum ref="ENUM194" /> + <use-enum ref="ENUM193" /> </bitfield> <bitfield name="ALPHA_SWIZ_C" high="29" low="27"> <doc>Specifies, per channel, the sources for RGB and Alpha input C.</doc> - <use-enum ref="ENUM195" /> + <use-enum ref="ENUM194" /> </bitfield> <bitfield name="ALPHA_MOD_C" high="31" low="30"> <doc>Specifies the input modifiers for RGB and Alpha input C.</doc> @@ -4670,22 +4486,22 @@ </stripe> <stripe offset="0xA000" stride="0x0004" length="512"> <reg32 name="US_ALU_RGB_INST" access="rw" offset="0x0000"> - <doc>ALU RGB Instruction</doc> + <doc>ALU RGB Instruction</doc> <bitfield name="RGB_SEL_A" high="1" low="0"> <doc>Specifies the operands for RGB inputs A and B.</doc> - <use-enum ref="ENUM194" /> + <use-enum ref="ENUM193" /> </bitfield> <bitfield name="RED_SWIZ_A" high="4" low="2"> <doc>Specifies, per channel, the sources for RGB inputs A and B.</doc> - <use-enum ref="ENUM195" /> + <use-enum ref="ENUM194" /> </bitfield> <bitfield name="GREEN_SWIZ_A" high="7" low="5"> <doc>Specifies, per channel, the sources for RGB inputs A and B.</doc> - <use-enum ref="ENUM195" /> + <use-enum ref="ENUM194" /> </bitfield> <bitfield name="BLUE_SWIZ_A" high="10" low="8"> <doc>Specifies, per channel, the sources for RGB inputs A and B.</doc> - <use-enum ref="ENUM195" /> + <use-enum ref="ENUM194" /> </bitfield> <bitfield name="RGB_MOD_A" high="12" low="11"> <doc>Specifies the input modifiers for RGB inputs A and B.</doc> @@ -4693,19 +4509,19 @@ </bitfield> <bitfield name="RGB_SEL_B" high="14" low="13"> <doc>Specifies the operands for RGB inputs A and B.</doc> - <use-enum ref="ENUM194" /> + <use-enum ref="ENUM193" /> </bitfield> <bitfield name="RED_SWIZ_B" high="17" low="15"> <doc>Specifies, per channel, the sources for RGB inputs A and B.</doc> - <use-enum ref="ENUM195" /> + <use-enum ref="ENUM194" /> </bitfield> <bitfield name="GREEN_SWIZ_B" high="20" low="18"> <doc>Specifies, per channel, the sources for RGB inputs A and B.</doc> - <use-enum ref="ENUM195" /> + <use-enum ref="ENUM194" /> </bitfield> <bitfield name="BLUE_SWIZ_B" high="23" low="21"> <doc>Specifies, per channel, the sources for RGB inputs A and B.</doc> - <use-enum ref="ENUM195" /> + <use-enum ref="ENUM194" /> </bitfield> <bitfield name="RGB_MOD_B" high="25" low="24"> <doc>Specifies the input modifiers for RGB inputs A and B.</doc> @@ -4713,48 +4529,48 @@ </bitfield> <bitfield name="OMOD" high="28" low="26"> <doc>Specifies the output modifier for this instruction.</doc> - <use-enum ref="ENUM196" /> + <use-enum ref="ENUM195" /> </bitfield> <bitfield name="TARGET" high="30" low="29"> <doc>This specifies which (cached) frame buffer target to write to. For non-output ALU instructions, this specifies how to compare the results against zero when setting the predicate bits.</doc> - <use-enum ref="ENUM197" /> + <use-enum ref="ENUM196" /> </bitfield> <bitfield name="ALU_WMASK" high="31" low="31"> <doc>Specifies whether to update the current ALU result.</doc> <value value="0" name="DO_NOT_MODIFY_THE_CURRENT_ALU_RESULT"><doc>Do not modify the current ALU result.</doc></value> - <value value="1" name="MODIFY_THE_CURRENT_ALU_RESULT_BASED_ON_THE"><doc>Modify the current ALU result based on the</doc></value> + <value value="1" name="MODIFY_THE_CURRENT_ALU_RESULT_BASED_ON_THE_SETTINGS_OF_ALU_RESULT_SEL_AND_ALU_RESULT_OP"><doc>Modify the current ALU result based on the settings of ALU_RESULT_SEL and ALU_RESULT_OP.</doc></value> </bitfield> </reg32> </stripe> <stripe offset="0x9000" stride="0x0004" length="512"> <reg32 name="US_ALU_RGB_ADDR" access="rw" offset="0x0000"> - <doc>This table specifies the RGB source addresses and pre-subtract operation for up to 512 ALU instructions. The ALU expects 6 source operands - three for color (rgb0, rgb1, rgb2) and three for alpha (a0, a1, a2). The pre-subtract operation creates two more (rgbp and ap).</doc> + <doc>This table specifies the RGB source addresses and pre-subtract operation for up to 512 ALU instructions. The ALU expects 6 source operands - three for color (rgb0, rgb1, rgb2) and three for alpha (a0, a1, a2). The pre-subtract operation creates two more (rgbp and ap).</doc> <bitfield name="ADDR0" high="7" low="0"><doc>Specifies the identity of source operands rgb0, rgb1, and rgb2. If the const field is set, this number ranges from 0 to 255 and specifies a location within the constant register bank. Otherwise: If the most significant bit is cleared, this field specifies a location within the current pixel stack frame (ranging from 0 to 127). If the most significant bit is set, then the lower 7 bits specify an inline unsigned floating-point constant with 4 bit exponent (bias 7) and 3 bit mantissa, including denormals but excluding infinite/NaN.</doc></bitfield> <bitfield name="ADDR0_CONST" high="8" low="8"> <doc>Specifies whether the associated address is a constant register address or a temporary address / inline constant.</doc> - <use-enum ref="ENUM199" /> + <use-enum ref="ENUM198" /> </bitfield> <bitfield name="ADDR0_REL" high="9" low="9"> <doc>Specifies whether the loop register is added to the value of the associated address before it is used. This implements relative addressing.</doc> - <use-enum ref="ENUM200" /> + <use-enum ref="ENUM199" /> </bitfield> <bitfield name="ADDR1" high="17" low="10"><doc>Specifies the identity of source operands rgb0, rgb1, and rgb2. If the const field is set, this number ranges from 0 to 255 and specifies a location within the constant register bank. Otherwise: If the most significant bit is cleared, this field specifies a location within the current pixel stack frame (ranging from 0 to 127). If the most significant bit is set, then the lower 7 bits specify an inline unsigned floating-point constant with 4 bit exponent (bias 7) and 3 bit mantissa, including denormals but excluding infinite/NaN.</doc></bitfield> <bitfield name="ADDR1_CONST" high="18" low="18"> <doc>Specifies whether the associated address is a constant register address or a temporary address / inline constant.</doc> - <use-enum ref="ENUM199" /> + <use-enum ref="ENUM198" /> </bitfield> <bitfield name="ADDR1_REL" high="19" low="19"> <doc>Specifies whether the loop register is added to the value of the associated address before it is used. This implements relative addressing.</doc> - <use-enum ref="ENUM200" /> + <use-enum ref="ENUM199" /> </bitfield> <bitfield name="ADDR2" high="27" low="20"><doc>Specifies the identity of source operands rgb0, rgb1, and rgb2. If the const field is set, this number ranges from 0 to 255 and specifies a location within the constant register bank. Otherwise: If the most significant bit is cleared, this field specifies a location within the current pixel stack frame (ranging from 0 to 127). If the most significant bit is set, then the lower 7 bits specify an inline unsigned floating-point constant with 4 bit exponent (bias 7) and 3 bit mantissa, including denormals but excluding infinite/NaN.</doc></bitfield> <bitfield name="ADDR2_CONST" high="28" low="28"> <doc>Specifies whether the associated address is a constant register address or a temporary address / inline constant.</doc> - <use-enum ref="ENUM199" /> + <use-enum ref="ENUM198" /> </bitfield> <bitfield name="ADDR2_REL" high="29" low="29"> <doc>Specifies whether the loop register is added to the value of the associated address before it is used. This implements relative addressing.</doc> - <use-enum ref="ENUM200" /> + <use-enum ref="ENUM199" /> </bitfield> <bitfield name="SRCP_OP" high="31" low="30"> <doc>Specifies how the pre-subtract value (SRCP) is computed.</doc> @@ -4764,41 +4580,41 @@ </stripe> <stripe offset="0xB800" stride="0x0004" length="512"> <reg32 name="US_CMN_INST" access="rw" offset="0x0000"> - <doc>Shared instruction fields for all instruction types</doc> + <doc>Shared instruction fields for all instruction types</doc> <bitfield name="TYPE" high="1" low="0"> <doc>Specifies the type of instruction. Note that output instructions write to render targets.</doc> - <value value="0" name="US_INST_TYPE_ALU"><doc>US_INST_TYPE_ALU: This instruction is an</doc></value> - <value value="1" name="US_INST_TYPE_OUT"><doc>US_INST_TYPE_OUT: This instruction is an</doc></value> - <value value="2" name="US_INST_TYPE_FC"><doc>US_INST_TYPE_FC: This instruction is a flow</doc></value> - <value value="3" name="US_INST_TYPE_TEX"><doc>US_INST_TYPE_TEX: This instruction is a</doc></value> + <value value="0" name="US_INST_TYPE_ALU"><doc>US_INST_TYPE_ALU: This instruction is an ALU instruction.</doc></value> + <value value="1" name="US_INST_TYPE_OUT"><doc>US_INST_TYPE_OUT: This instruction is an output instruction.</doc></value> + <value value="2" name="US_INST_TYPE_FC"><doc>US_INST_TYPE_FC: This instruction is a flow control instruction.</doc></value> + <value value="3" name="US_INST_TYPE_TEX"><doc>US_INST_TYPE_TEX: This instruction is a texture instruction.</doc></value> </bitfield> <bitfield name="TEX_SEM_WAIT" high="2" low="2"> <doc>Specifies whether to wait for the texture semaphore.</doc> <value value="0" name="THIS_INSTRUCTION_MAY_ISSUE_IMMEDIATELY"><doc>This instruction may issue immediately.</doc></value> - <value value="1" name="THIS_INSTRUCTION_WILL_NOT_ISSUE_UNTIL_THE_TEXTURE"><doc>This instruction will not issue until the texture</doc></value> + <value value="1" name="THIS_INSTRUCTION_WILL_NOT_ISSUE_UNTIL_THE_TEXTURE_SEMAPHORE_IS_AVAILABLE"><doc>This instruction will not issue until the texture semaphore is available.</doc></value> </bitfield> <bitfield name="RGB_PRED_SEL" high="5" low="3"> <doc>Specifies whether the instruction uses predication. For ALU/TEX/Output this specifies predication for the RGB channels only. For FC this specifies the predicate for the entire instruction.</doc> <value value="0" name="US_PRED_SEL_NONE"><doc>US_PRED_SEL_NONE: No predication</doc></value> - <value value="1" name="US_PRED_SEL_RGBA"><doc>US_PRED_SEL_RGBA: Independent Channel</doc></value> - <value value="2" name="US_PRED_SEL_RRRR"><doc>US_PRED_SEL_RRRR: R-Replicate</doc></value> - <value value="3" name="US_PRED_SEL_GGGG"><doc>US_PRED_SEL_GGGG: G-Replicate</doc></value> - <value value="4" name="US_PRED_SEL_BBBB"><doc>US_PRED_SEL_BBBB: B-Replicate</doc></value> - <value value="5" name="US_PRED_SEL_AAAA"><doc>US_PRED_SEL_AAAA: A-Replicate</doc></value> + <value value="1" name="US_PRED_SEL_RGBA"><doc>US_PRED_SEL_RGBA: Independent Channel Predication</doc></value> + <value value="2" name="US_PRED_SEL_RRRR"><doc>US_PRED_SEL_RRRR: R-Replicate Predication</doc></value> + <value value="3" name="US_PRED_SEL_GGGG"><doc>US_PRED_SEL_GGGG: G-Replicate Predication</doc></value> + <value value="4" name="US_PRED_SEL_BBBB"><doc>US_PRED_SEL_BBBB: B-Replicate Predication</doc></value> + <value value="5" name="US_PRED_SEL_AAAA"><doc>US_PRED_SEL_AAAA: A-Replicate Predication</doc></value> </bitfield> <bitfield name="RGB_PRED_INV" high="6" low="6"> <doc>Specifies whether the predicate should be inverted. For ALU/TEX/Output this specifies predication for the RGB channels only. For FC this specifies the predicate for the entire instruction.</doc> - <use-enum ref="ENUM206" /> + <use-enum ref="ENUM205" /> </bitfield> <bitfield name="WRITE_INACTIVE" high="7" low="7"> <doc>Specifies which pixels to write to.</doc> <value value="0" name="ONLY_WRITE_TO_CHANNELS_OF_ACTIVE_PIXELS"><doc>Only write to channels of active pixels</doc></value> - <value value="1" name="WRITE_TO_CHANNELS_OF_ALL_PIXELS"><doc>Write to channels of all pixels, including inactive</doc></value> + <value value="1" name="WRITE_TO_CHANNELS_OF_ALL_PIXELS"><doc>Write to channels of all pixels, including inactive pixels</doc></value> </bitfield> <bitfield name="LAST" high="8" low="8"> <doc>Specifies whether this is the last instruction.</doc> - <value value="0" name="DO_NOT_TERMINATE_THE_SHADER_AFTER_EXECUTING_THIS"><doc>Do not terminate the shader after executing this</doc></value> - <value value="1" name="ALL_ACTIVE_PIXELS_ARE_WILLING_TO_TERMINATE_AFTER"><doc>All active pixels are willing to terminate after</doc></value> + <value value="0" name="DO_NOT_TERMINATE_THE_SHADER_AFTER_EXECUTING_THIS_INSTRUCTION"><doc>Do not terminate the shader after executing this instruction (unless this instruction is at END_ADDR).</doc></value> + <value value="1" name="ALL_ACTIVE_PIXELS_ARE_WILLING_TO_TERMINATE_AFTER_EXECUTING_THIS_INSTRUCTION"><doc>All active pixels are willing to terminate after executing this instruction. There is no guarantee that the shader will actually terminate here. This feature is provided as a performance optimization for tests where pixels can conditionally terminate early.</doc></value> </bitfield> <bitfield name="NOP" high="9" low="9"> <doc>Specifies whether to insert a NOP instruction after this. This would get specified in order to meet dependency requirements for the pre-subtract inputs, and dependency requirements for src0 of an MDH/MDV instruction.</doc> @@ -4807,12 +4623,12 @@ </bitfield> <bitfield name="ALU_WAIT" high="10" low="10"> <doc>Specifies whether to wait for pending ALU instructions to complete before issuing this instruction.</doc> - <value value="0" name="DO_NOT_WAIT_FOR_PENDING_ALU_INSTRUCTIONS_TO"><doc>Do not wait for pending ALU instructions to</doc></value> - <value value="1" name="WAIT_FOR_PENDING_ALU_INSTRUCTIONS_TO_COMPLETE"><doc>Wait for pending ALU instructions to complete</doc></value> + <value value="0" name="DO_NOT_WAIT_FOR_PENDING_ALU_INSTRUCTIONS_TO_COMPLETE_BEFORE_ISSUING_THE_CURRENT_INSTRUCTION"><doc>Do not wait for pending ALU instructions to complete before issuing the current instruction.</doc></value> + <value value="1" name="WAIT_FOR_PENDING_ALU_INSTRUCTIONS_TO_COMPLETE_BEFORE_ISSUING_THE_CURRENT_INSTRUCTION"><doc>Wait for pending ALU instructions to complete before issuing the current instruction.</doc></value> </bitfield> <bitfield name="RGB_WMASK" high="13" low="11"> <doc>Specifies which components of the result of the RGB instruction are written to the pixel stack frame.</doc> - <use-enum ref="ENUM211" /> + <use-enum ref="ENUM210" /> </bitfield> <bitfield name="ALPHA_WMASK" high="14" low="14"> <doc>Specifies whether the result of the Alpha instruction is written to the pixel stack frame.</doc> @@ -4821,7 +4637,7 @@ </bitfield> <bitfield name="RGB_OMASK" high="17" low="15"> <doc>Specifies which components of the result of the RGB instruction are written to the output fifo if this is an output instruction, and which predicate bits should be modified if this is an ALU instruction.</doc> - <use-enum ref="ENUM211" /> + <use-enum ref="ENUM210" /> </bitfield> <bitfield name="ALPHA_OMASK" high="18" low="18"> <doc>Specifies whether the result of the Alpha instruction is written to the output fifo if this is an output instruction, and whether the Alpha predicate bit should be modified if this is an ALU instruction.</doc> @@ -4843,7 +4659,7 @@ </bitfield> <bitfield name="ALPHA_PRED_INV" high="22" low="22"> <doc>Specifies whether the predicate should be inverted. For ALU/TEX/Output this specifies predication for the alpha channel only. This field has no effect on FC instructions.</doc> - <use-enum ref="ENUM206" /> + <use-enum ref="ENUM205" /> </bitfield> <bitfield name="ALU_RESULT_OP" high="24" low="23"> <doc>Specifies how to compare the ALU result against zero for the `alu_result` bit in a subsequent flow control instruction.</doc> @@ -4855,7 +4671,7 @@ <bitfield name="ALPHA_PRED_SEL" high="27" low="25"> <doc>Specifies whether the instruction uses predication. For ALU/TEX/Output this specifies predication for the alpha channel only. This field has no effect on FC instructions.</doc> <value value="0" name="US_PRED_SEL_NONE"><doc>US_PRED_SEL_NONE: No predication</doc></value> - <value value="1" name="US_PRED_SEL_RGBA"><doc>US_PRED_SEL_RGBA: A predication</doc></value> + <value value="1" name="US_PRED_SEL_RGBA"><doc>US_PRED_SEL_RGBA: A predication (identical to US_PRED_SEL_AAAA)</doc></value> <value value="2" name="US_PRED_SEL_RRRR"><doc>US_PRED_SEL_RRRR: R Predication</doc></value> <value value="3" name="US_PRED_SEL_GGGG"><doc>US_PRED_SEL_GGGG: G Predication</doc></value> <value value="4" name="US_PRED_SEL_BBBB"><doc>US_PRED_SEL_BBBB: B Predication</doc></value> @@ -4884,19 +4700,19 @@ <bitfield name="ZERO_TIMES_ANYTHING_EQUALS_ZERO" high="1" low="1"> <doc>Control how ALU multiplier behaves when one argument is zero. This affects the multiplier used in MAD and dot product calculations.</doc> <value value="0" name="DEFAULT_BEHAVIOUR"><doc>Default behaviour (0*inf=nan,0*nan=nan)</doc></value> - <value value="1" name="LEGACY_BEHAVIOUR_FOR_SHADER_MODEL_1"><doc>Legacy behaviour for shader model 1</doc></value> + <value value="1" name="LEGACY_BEHAVIOUR_FOR_SHADER_MODEL_1"><doc>Legacy behaviour for shader model 1 (0*anything=0)</doc></value> </bitfield> </reg32> <stripe offset="0xA000" stride="0x0004" length="512"> <reg32 name="US_FC_ADDR" access="rw" offset="0x0000"> - <doc>Flow Control Instruction Address Fields</doc> + <doc>Flow Control Instruction Address Fields</doc> <bitfield name="BOOL_ADDR" high="4" low="0"><doc>The address of the static boolean register to use in the jump function.</doc></bitfield> <bitfield name="INT_ADDR" high="12" low="8"><doc>The address of the static integer register to use for loop/rep and endloop/endrep.</doc></bitfield> <bitfield name="JUMP_ADDR" high="24" low="16"><doc>The address to jump to if the jump function evaluates to true.</doc></bitfield> <bitfield name="JUMP_GLOBAL" high="31" low="31"> <doc>Specifies whether to interpret JUMP_ADDR as a global address.</doc> - <value value="0" name="ADD_THE_SHADER_PROGRAM_OFFSET_IN"><doc>Add the shader program offset in</doc></value> - <value value="1" name="DON"><doc>Don`t use the shader program offset when</doc></value> + <value value="0" name="ADD_THE_SHADER_PROGRAM_OFFSET_IN_US_CODE_OFFSET"><doc>Add the shader program offset in US_CODE_OFFSET.OFFSET_ADDR when calculating the destination address of a jump</doc></value> + <value value="1" name="DON"><doc>Don`t use the shader program offset when calculating the destination address jump</doc></value> </bitfield> </reg32> </stripe> @@ -4912,64 +4728,64 @@ </bitfield> <bitfield name="FULL_FC_EN" high="31" low="31"> <doc>Specifies whether full flow control functionality is enabled.</doc> - <value value="0" name="USE_PARTIAL_FLOW"><doc>Use partial flow-control (enables twice the</doc></value> - <value value="1" name="USE_FULL_PIXEL_SHADER_3"><doc>Use full pixel shader 3.0 flow control, including</doc></value> + <value value="0" name="USE_PARTIAL_FLOW"><doc>Use partial flow-control (enables twice the contexts). Loops and subroutines are not available in partial flow-control mode, and the nesting depth of branch statements is limited.</doc></value> + <value value="1" name="USE_FULL_PIXEL_SHADER_3"><doc>Use full pixel shader 3.0 flow control, including loops and subroutines.</doc></value> </bitfield> </reg32> <stripe offset="0x9800" stride="0x0004" length="512"> <reg32 name="US_FC_INST" access="rw" offset="0x0000"> - <doc>Flow Control Instruction</doc> + <doc>Flow Control Instruction</doc> <bitfield name="OP" high="2" low="0"> <doc>Specifies the type of flow control instruction.</doc> <value value="0" name="US_FC_OP_JUMP"><doc>US_FC_OP_JUMP: (if, endif, call, etc)</doc></value> - <value value="1" name="US_FC_OP_LOOP"><doc>US_FC_OP_LOOP: same as jump except</doc></value> - <value value="2" name="US_FC_OP_ENDLOOP"><doc>US_FC_OP_ENDLOOP: same as jump but</doc></value> - <value value="3" name="US_FC_OP_REP"><doc>US_FC_OP_REP: same as loop but don`t push</doc></value> - <value value="4" name="US_FC_OP_ENDREP"><doc>US_FC_OP_ENDREP: same as endloop but</doc></value> - <value value="5" name="US_FC_OP_BREAKLOOP"><doc>US_FC_OP_BREAKLOOP: same as jump but</doc></value> - <value value="6" name="US_FC_OP_BREAKREP"><doc>US_FC_OP_BREAKREP: same as breakloop</doc></value> - <value value="7" name="US_FC_OP_CONTINUE"><doc>US_FC_OP_CONTINUE: used to disable pixels</doc></value> + <value value="1" name="US_FC_OP_LOOP"><doc>US_FC_OP_LOOP: same as jump except always take the jump if the static counter is 0. If we don`t take the jump, push initial loop counter and loop register (aL) values onto the loop stack.</doc></value> + <value value="2" name="US_FC_OP_ENDLOOP"><doc>US_FC_OP_ENDLOOP: same as jump but decrement the loop counter and increment the loop register (aL), and don`t take the jump if the loop counter becomes zero.</doc></value> + <value value="3" name="US_FC_OP_REP"><doc>US_FC_OP_REP: same as loop but don`t push the loop register aL.</doc></value> + <value value="4" name="US_FC_OP_ENDREP"><doc>US_FC_OP_ENDREP: same as endloop but don`t update/pop the loop register aL.</doc></value> + <value value="5" name="US_FC_OP_BREAKLOOP"><doc>US_FC_OP_BREAKLOOP: same as jump but pops the loop stacks if a pixel stops being active.</doc></value> + <value value="6" name="US_FC_OP_BREAKREP"><doc>US_FC_OP_BREAKREP: same as breakloop but don`t pop the loop register if it jumps.</doc></value> + <value value="7" name="US_FC_OP_CONTINUE"><doc>US_FC_OP_CONTINUE: used to disable pixels that are ready to jump to the ENDLOOP/ENDREP instruction.</doc></value> </bitfield> <bitfield name="B_ELSE" high="4" low="4"> <doc>Specifies whether to perform an else operation on the active and branch-inactive pixels before executing the instruction.</doc> - <value value="0" name="DON"><doc>Don`t alter the branch state before executing the</doc></value> - <value value="1" name="PERFORM_AN_ELSE_OPERATION_ON_THE_BRANCH_STATE"><doc>Perform an else operation on the branch state</doc></value> + <value value="0" name="DON"><doc>Don`t alter the branch state before executing the instruction.</doc></value> + <value value="1" name="PERFORM_AN_ELSE_OPERATION_ON_THE_BRANCH_STATE_BEFORE_EXECUTING_THE_INSTRUCTION"><doc>Perform an else operation on the branch state before executing the instruction; pixels in the active state are moved to the branch inactive state with zero counter, and vice versa.</doc></value> </bitfield> <bitfield name="JUMP_ANY" high="5" low="5"> <doc>If set, jump if any active pixels want to take the jump (otherwise the instruction jumps only if all active pixels want to).</doc> - <value value="0" name="JUMP_IF_ALL_ACTIVE_PIXELS_WANT_TO_TAKE_THE_JUMP"><doc>Jump if ALL active pixels want to take the jump</doc></value> - <value value="1" name="JUMP_IF_ANY_ACTIVE_PIXELS_WANT_TO_TAKE_THE_JUMP"><doc>Jump if ANY active pixels want to take the jump</doc></value> + <value value="0" name="JUMP_IF_ALL_ACTIVE_PIXELS_WANT_TO_TAKE_THE_JUMP"><doc>Jump if ALL active pixels want to take the jump (for if and else). If no pixels are active, jump.</doc></value> + <value value="1" name="JUMP_IF_ANY_ACTIVE_PIXELS_WANT_TO_TAKE_THE_JUMP"><doc>Jump if ANY active pixels want to take the jump (for call, loop/rep and endrep/endloop). If no pixels are active, do not jump.</doc></value> </bitfield> <bitfield name="A_OP" high="7" low="6"> <doc>The address stack operation to perform if we take the jump.</doc> - <value value="0" name="US_FC_A_OP_NONE"><doc>US_FC_A_OP_NONE: Don`t change the</doc></value> - <value value="1" name="US_FC_A_OP_POP"><doc>US_FC_A_OP_POP: If we jump, pop the</doc></value> - <value value="2" name="US_FC_A_OP_PUSH"><doc>US_FC_A_OP_PUSH: If we jump, push the</doc></value> + <value value="0" name="US_FC_A_OP_NONE"><doc>US_FC_A_OP_NONE: Don`t change the address stack</doc></value> + <value value="1" name="US_FC_A_OP_POP"><doc>US_FC_A_OP_POP: If we jump, pop the address stack and use that value for the jump target</doc></value> + <value value="2" name="US_FC_A_OP_PUSH"><doc>US_FC_A_OP_PUSH: If we jump, push the current address onto the address stack</doc></value> </bitfield> <bitfield name="JUMP_FUNC" high="15" low="8"><doc>A 2x2x2 table of boolean values indicating whether to take the jump. The table index is indexed by {ALU Compare Result, Predication Result, Boolean Value (from the static boolean address in US_FC_ADDR.BOOL)}. To determine whether to jump, look at bit ((alu_result<<2) | (predicate<<1) | bool).</doc></bitfield> <bitfield name="B_POP_CNT" high="20" low="16"><doc>The amount to decrement the branch counter by if US_FC_B_OP_DECR operation is performed.</doc></bitfield> <bitfield name="B_OP0" high="25" low="24"> <doc>The branch state operation to perform if we don`t take the jump.</doc> - <value value="0" name="US_FC_B_OP_NONE"><doc>US_FC_B_OP_NONE: If we don`t jump, don`t</doc></value> - <value value="1" name="US_FC_B_OP_DECR"><doc>US_FC_B_OP_DECR: If we don`t jump,</doc></value> - <value value="2" name="US_FC_B_OP_INCR"><doc>US_FC_B_OP_INCR: If we don`t jump,</doc></value> + <value value="0" name="US_FC_B_OP_NONE"><doc>US_FC_B_OP_NONE: If we don`t jump, don`t alter the branch counter for any pixel.</doc></value> + <value value="1" name="US_FC_B_OP_DECR"><doc>US_FC_B_OP_DECR: If we don`t jump, decrement branch counter by B_POP_CNT for inactive pixels. Activate pixels with negative counters.</doc></value> + <value value="2" name="US_FC_B_OP_INCR"><doc>US_FC_B_OP_INCR: If we don`t jump, increment branch counter by 1 for inactive pixels. Deactivate pixels that decided to jump and set their counter to zero.</doc></value> </bitfield> <bitfield name="B_OP1" high="27" low="26"> <doc>The branch state operation to perform if we do take the jump.</doc> - <value value="0" name="US_FC_B_OP_NONE"><doc>US_FC_B_OP_NONE: If we do jump, don`t</doc></value> - <value value="1" name="US_FC_B_OP_DECR"><doc>US_FC_B_OP_DECR: If we do jump,</doc></value> - <value value="2" name="US_FC_B_OP_INCR"><doc>US_FC_B_OP_INCR: If we do jump, increment</doc></value> + <value value="0" name="US_FC_B_OP_NONE"><doc>US_FC_B_OP_NONE: If we do jump, don`t alter the branch counter for any pixel.</doc></value> + <value value="1" name="US_FC_B_OP_DECR"><doc>US_FC_B_OP_DECR: If we do jump, decrement branch counter by B_POP_CNT for inactive pixels. Activate pixels with negative counters.</doc></value> + <value value="2" name="US_FC_B_OP_INCR"><doc>US_FC_B_OP_INCR: If we do jump, increment branch counter by 1 for inactive pixels. Deactivate pixels that decided not to jump and set their counter to zero.</doc></value> </bitfield> <bitfield name="IGNORE_UNCOVERED" high="28" low="28"> <doc>If set, uncovered pixels will not participate in flow control decisions.</doc> <value value="0" name="INCLUDE_UNCOVERED_PIXELS_IN_JUMP_DECISIONS"><doc>Include uncovered pixels in jump decisions</doc></value> - <value value="1" name="IGNORE_UNCOVERED_PIXELS_IN_MAKING_JUMP"><doc>Ignore uncovered pixels in making jump</doc></value> + <value value="1" name="IGNORE_UNCOVERED_PIXELS_IN_MAKING_JUMP_DECISIONS"><doc>Ignore uncovered pixels in making jump decisions</doc></value> </bitfield> </reg32> </stripe> <stripe offset="0x4C00" stride="0x0004" length="32"> <reg32 name="US_FC_INT_CONST" access="rw" offset="0x0000"> - <doc>Integer Constants used by Flow Control Loop Instructions. Single buffered.</doc> + <doc>Integer Constants used by Flow Control Loop Instructions. Single buffered.</doc> <bitfield name="KR" high="7" low="0"><doc>Specifies the number of iterations. Unsigned 8-bit integer in [0, 255].</doc></bitfield> <bitfield name="KG" high="15" low="8"><doc>Specifies the initial value of the loop register (aL). Unsigned 8-bit integer in [0, 255].</doc></bitfield> <bitfield name="KB" high="23" low="16"><doc>Specifies the increment used to change the loop register (aL) on each iteration. Signed 7-bit integer in [-128, 127].</doc></bitfield> @@ -4977,9 +4793,7 @@ </stripe> <stripe offset="0x4640" stride="0x0004" length="16"> <reg32 name="US_FORMAT0" access="rw" offset="0x0000"> - <doc></doc> <bitfield name="TXDEPTH" high="25" low="22"> - <doc></doc> <value value="13" name="WIDTH"><doc>width > 2048, height <= 2048</doc></value> <value value="14" name="WIDTH"><doc>width <= 2048, height > 2048</doc></value> <value value="15" name="WIDTH"><doc>width > 2048, height > 2048</doc></value> @@ -4988,29 +4802,12 @@ </stripe> <stripe offset="0x46A4" stride="0x0004" length="4"> <reg32 name="US_OUT_FMT" access="rw" offset="0x0000"> - <doc></doc> - <bitfield name="OUT_FMT" high="4" low="0"> - <doc></doc> - <use-enum ref="ENUM109" /> - </bitfield> - <bitfield name="C0_SEL" high="9" low="8"> - <doc></doc> - <use-enum ref="ENUM110" /> - </bitfield> - <bitfield name="C1_SEL" high="11" low="10"> - <doc></doc> - <use-enum ref="ENUM110" /> - </bitfield> - <bitfield name="C2_SEL" high="13" low="12"> - <doc></doc> - <use-enum ref="ENUM110" /> - </bitfield> - <bitfield name="C3_SEL" high="15" low="14"> - <doc></doc> - <use-enum ref="ENUM110" /> - </bitfield> + <bitfield name="OUT_FMT" high="4" low="0"><use-enum ref="ENUM109" /></bitfield> + <bitfield name="C0_SEL" high="9" low="8"><use-enum ref="ENUM110" /></bitfield> + <bitfield name="C1_SEL" high="11" low="10"><use-enum ref="ENUM110" /></bitfield> + <bitfield name="C2_SEL" high="13" low="12"><use-enum ref="ENUM110" /></bitfield> + <bitfield name="C3_SEL" high="15" low="14"><use-enum ref="ENUM110" /></bitfield> <bitfield name="ROUND_ADJ" high="20" low="20"> - <doc></doc> <value value="0" name="NORMAL_ROUNDING"><doc>Normal rounding</doc></value> <value value="1" name="MODIFIED_ROUNDING_OF_FIXED"><doc>Modified rounding of fixed-point data</doc></value> </bitfield> @@ -5022,27 +4819,27 @@ </reg32> <stripe offset="0x9800" stride="0x0004" length="512"> <reg32 name="US_TEX_ADDR" access="rw" offset="0x0000"> - <doc>Texture addresses and swizzles</doc> + <doc>Texture addresses and swizzles</doc> <bitfield name="SRC_ADDR" high="6" low="0"><doc>Specifies the location (within the shader pixel stack frame) of the texture address for this instruction</doc></bitfield> <bitfield name="SRC_ADDR_REL" high="7" low="7"> <doc>Specifies whether the loop register is added to the value of the associated address before it is used. This implements relative addressing.</doc> - <use-enum ref="ENUM230" /> + <use-enum ref="ENUM229" /> </bitfield> <bitfield name="SRC_S_SWIZ" high="9" low="8"> <doc>Specify which colour channel of src_addr to use for S coordinate</doc> - <use-enum ref="ENUM231" /> + <use-enum ref="ENUM230" /> </bitfield> <bitfield name="SRC_T_SWIZ" high="11" low="10"> <doc>Specify which colour channel of src_addr to use for T coordinate</doc> - <use-enum ref="ENUM232" /> + <use-enum ref="ENUM231" /> </bitfield> <bitfield name="SRC_R_SWIZ" high="13" low="12"> <doc>Specify which colour channel of src_addr to use for R coordinate</doc> - <use-enum ref="ENUM233" /> + <use-enum ref="ENUM232" /> </bitfield> <bitfield name="SRC_Q_SWIZ" high="15" low="14"> <doc>Specify which colour channel of src_addr to use for Q coordinate</doc> - <use-enum ref="ENUM234" /> + <use-enum ref="ENUM233" /> </bitfield> <bitfield name="DST_ADDR" high="22" low="16"><doc>Specifies the location (within the shader pixel stack frame) of the returned texture data for this instruction</doc></bitfield> <bitfield name="DST_ADDR_REL" high="23" low="23"> @@ -5082,69 +4879,69 @@ </stripe> <stripe offset="0xA000" stride="0x0004" length="512"> <reg32 name="US_TEX_ADDR_DXDY" access="rw" offset="0x0000"> - <doc>Additional texture addresses and swizzles for DX/DY inputs</doc> + <doc>Additional texture addresses and swizzles for DX/DY inputs</doc> <bitfield name="DX_ADDR" high="6" low="0"><doc>Specifies the location (within the shader pixel stack frame) of the DX value for this instruction</doc></bitfield> <bitfield name="DX_ADDR_REL" high="7" low="7"> <doc>Specifies whether the loop register is added to the value of the associated address before it is used. This implements relative addressing.</doc> - <use-enum ref="ENUM230" /> + <use-enum ref="ENUM229" /> </bitfield> <bitfield name="DX_S_SWIZ" high="9" low="8"> <doc>Specify which colour channel of dx_addr to use for S coordinate</doc> - <use-enum ref="ENUM231" /> + <use-enum ref="ENUM230" /> </bitfield> <bitfield name="DX_T_SWIZ" high="11" low="10"> <doc>Specify which colour channel of dx_addr to use for T coordinate</doc> - <use-enum ref="ENUM232" /> + <use-enum ref="ENUM231" /> </bitfield> <bitfield name="DX_R_SWIZ" high="13" low="12"> <doc>Specify which colour channel of dx_addr to use for R coordinate</doc> - <use-enum ref="ENUM233" /> + <use-enum ref="ENUM232" /> </bitfield> <bitfield name="DX_Q_SWIZ" high="15" low="14"> <doc>Specify which colour channel of dx_addr to use for Q coordinate</doc> - <use-enum ref="ENUM234" /> + <use-enum ref="ENUM233" /> </bitfield> <bitfield name="DY_ADDR" high="22" low="16"><doc>Specifies the location (within the shader pixel stack frame) of the DY value for this instruction</doc></bitfield> <bitfield name="DY_ADDR_REL" high="23" low="23"> <doc>Specifies whether the loop register is added to the value of the associated address before it is used. This implements relative addressing.</doc> - <use-enum ref="ENUM230" /> + <use-enum ref="ENUM229" /> </bitfield> <bitfield name="DY_S_SWIZ" high="25" low="24"> <doc>Specify which colour channel of dy_addr to use for S coordinate</doc> - <use-enum ref="ENUM231" /> + <use-enum ref="ENUM230" /> </bitfield> <bitfield name="DY_T_SWIZ" high="27" low="26"> <doc>Specify which colour channel of dy_addr to use for T coordinate</doc> - <use-enum ref="ENUM232" /> + <use-enum ref="ENUM231" /> </bitfield> <bitfield name="DY_R_SWIZ" high="29" low="28"> <doc>Specify which colour channel of dy_addr to use for R coordinate</doc> - <use-enum ref="ENUM233" /> + <use-enum ref="ENUM232" /> </bitfield> <bitfield name="DY_Q_SWIZ" high="31" low="30"> <doc>Specify which colour channel of dy_addr to use for Q coordinate</doc> - <use-enum ref="ENUM234" /> + <use-enum ref="ENUM233" /> </bitfield> </reg32> </stripe> <stripe offset="0x9000" stride="0x0004" length="512"> <reg32 name="US_TEX_INST" access="rw" offset="0x0000"> - <doc>Texture Instruction</doc> + <doc>Texture Instruction</doc> <bitfield name="TEX_ID" high="19" low="16"><doc>Specifies the id of the texture map used for this instruction</doc></bitfield> <bitfield name="INST" high="24" low="22"> <doc>Specifies the operation taking place for this instruction</doc> <value value="0" name="NOP"><doc>NOP: Do nothing</doc></value> <value value="1" name="LD"><doc>LD: Do Texture Lookup (S,T,R)</doc></value> <value value="2" name="TEXKILL"><doc>TEXKILL: Kill pixel if any component is < 0</doc></value> - <value value="3" name="PROJ"><doc>PROJ: Do projected texture lookup</doc></value> + <value value="3" name="PROJ"><doc>PROJ: Do projected texture lookup (S/Q,T/Q,R/Q)</doc></value> <value value="4" name="LODBIAS"><doc>LODBIAS: Do texture lookup with lod bias</doc></value> <value value="5" name="LOD"><doc>LOD: Do texture lookup with explicit lod</doc></value> - <value value="6" name="DXDY"><doc>DXDY: Do texture lookup with lod calculated</doc></value> + <value value="6" name="DXDY"><doc>DXDY: Do texture lookup with lod calculated from DX and DY</doc></value> </bitfield> <bitfield name="TEX_SEM_ACQUIRE" high="25" low="25"> <doc>Whether to hold the texture semaphore until the data is written to the temporary register.</doc> <value value="0" name="DON"><doc>Don`t hold the texture semaphore</doc></value> - <value value="1" name="HOLD_THE_TEXTURE_SEMAPHORE_UNTIL_THE_DATA_IS"><doc>Hold the texture semaphore until the data is</doc></value> + <value value="1" name="HOLD_THE_TEXTURE_SEMAPHORE_UNTIL_THE_DATA_IS_WRITTEN_TO_THE_TEMPORARY_REGISTER"><doc>Hold the texture semaphore until the data is written to the temporary register.</doc></value> </bitfield> <bitfield name="IGNORE_UNCOVERED" high="26" low="26"> <doc>If set, US will not request data for pixels which are uncovered. Clear this bit for indirect texture lookups.</doc> @@ -5153,7 +4950,7 @@ </bitfield> <bitfield name="UNSCALED" high="27" low="27"> <doc>Whether to scale texture coordinates when sending them to the texture unit.</doc> - <value value="0" name="SCALE_THE_S"><doc>Scale the S, T, R texture coordinates from</doc></value> + <value value="0" name="SCALE_THE_S"><doc>Scale the S, T, R texture coordinates from [0.0,1.0] to the dimensions of the target texture</doc></value> <value value="1" name="USE_THE_UNSCALED_S"><doc>Use the unscaled S, T, R texture coordates.</doc></value> </bitfield> </reg32> @@ -5164,7 +4961,7 @@ <doc>Format for W</doc> <value value="0" name="W0"><doc>W0 - W is always zero</doc></value> <value value="1" name="W24"><doc>W24 - 24-bit fixed point</doc></value> - <value value="2" name="W24_FP"><doc>W24_FP - 24-bit floating point. The floating</doc></value> + <value value="2" name="W24_FP"><doc>W24_FP - 24-bit floating point. The floating point values are a special format that preserve sorting order when values are compared as integers, allowing higher precision in W without additional logic in other blocks.</doc></value> </bitfield> <bitfield name="W_SRC" high="2" low="2"> <doc>Source for W</doc> @@ -5224,7 +5021,7 @@ </reg32> <stripe offset="0x2150" stride="0x0004" length="8"> <reg32 name="VAP_PROG_STREAM_CNTL" access="rw" offset="0x0000"> - <doc>Programmable Stream Control Word 0</doc> + <doc>Programmable Stream Control Word 0</doc> <bitfield name="DATA_TYPE_0" high="3" low="0"><doc>The data type for element 0 0 = FLOAT_1 (Single IEEE Float) 1 = FLOAT_2 (2 IEEE floats) 2 = FLOAT_3 (3 IEEE Floats) 3 = FLOAT_4 (4 IEEE Floats) 4 = BYTE * (1 DWORD w 4 8-bit fixed point values) (X = [7:0], Y = [15:8], Z = [23:16], W = [31:24]) 5 = D3DCOLOR * (Same as BYTE except has X->Z,Z- >X swap for D3D color def) (Z = [7:0], Y = [15:8], X = [23:16], W = [31:24]) 6 = SHORT_2 * (1 DWORD with 2 16-bit fixed point values) (X = [15:0], Y = [31:16], Z = 0.0, W = 1.0) 7 = SHORT_4 * (2 DWORDS with 4(2 per dword) 16- bit fixed point values) (X = DW0 [15:0], Y = DW0 [31:16], Z = DW1 [15:0], W = DW1 [31:16]) 8 = VECTOR_3_TTT * (1 DWORD with 3 10-bit fixed point values) (X = [9:0], Y = [19:10], Z = [29:20], W = 1.0) 9 = VECTOR_3_EET * (1 DWORD with 2 11-bit and 1 10-bit fixed point values) (X = [10:0], Y = [21:11], Z = [31:22], W = 1.0) 10 = FLOAT_8 (8 IEEE Floats) Sames as 2 FLOAT_4 but must use consecutive DST_VEC_LOC. Used to allow > 16 PSC for OGL path. 11 = FLT16_2 (1 DWORD with 2 16-bit floating point values (SE5M10 exp bias of 15, supports denormalized numbers)) (X = [15:0], Y = [31:16], Z = 0.0, W = 1.0) 12 = FLT16_4 (2 DWORDS with 4(2 per dword) 16-bit floating point values (SE5M10 exp bias of 15, supports denormalized numbers))) (X = DW0 [15:0], Y = DW0 [31:16], Z = DW1 [15:0], W = DW1 [31:16]) * These data types use the SIGNED and NORMALIZE flags described below.</doc></bitfield> <bitfield name="SKIP_DWORDS_0" high="7" low="4"><doc>The number of DWORDS to skip (discard) after processing the current element.</doc></bitfield> <bitfield name="DST_VEC_LOC_0" high="12" low="8"><doc>The vector address in the input memory to write this element</doc></bitfield> @@ -5244,33 +5041,33 @@ </stripe> <stripe offset="0x2500" stride="0x0008" length="16"> <reg32 name="VAP_PVS_FLOW_CNTL_ADDRS_LW" access="rw" offset="0x0000"> - <doc>For VS3.0 - To support more PVS instructions, increase the address range - Programmable Vertex Shader Flow Control Lower Word Addresses Register 0</doc> + <doc>For VS3.0 - To support more PVS instructions, increase the address range - Programmable Vertex Shader Flow Control Lower Word Addresses Register 0</doc> <bitfield name="PVS_FC_ACT_ADRS_0" high="15" low="0"> <doc>This field defines the last PVS instruction to execute prior to the control flow redirection. JUMP - The last instruction executed prior to the jump LOOP - The last instruction executed prior to the loop (init loop counter/inc) JSR - The last instruction executed prior to the jump to the subroutine. (Addrss_Range:1K=[9:0];512=[8:0];256=[7:0])</doc> - <use-enum ref="ENUM245" /> + <use-enum ref="ENUM244" /> </bitfield> <bitfield name="PVS_FC_LOOP_CNT_JMP_INST_0" high="31" low="16"> <doc>This field has multiple definitions as follows: JUMP - The instruction address to jump to. LOOP - The loop count. *Note loop count of 0 must be replaced by a jump. JSR - The instruction address to jump to (first inst of subroutine). (Addrss_Range:1K=[24:15];512=[23:15];256=[22:15])</doc> - <use-enum ref="ENUM246" /> + <use-enum ref="ENUM245" /> </bitfield> </reg32> </stripe> <stripe offset="0x2504" stride="0x0008" length="16"> <reg32 name="VAP_PVS_FLOW_CNTL_ADDRS_UW" access="rw" offset="0x0000"> - <doc>For VS3.0 - To support more PVS instructions, increase the address range - Programmable Vertex Shader Flow Control Upper Word Addresses Register 0</doc> + <doc>For VS3.0 - To support more PVS instructions, increase the address range - Programmable Vertex Shader Flow Control Upper Word Addresses Register 0</doc> <bitfield name="PVS_FC_LAST_INST_0" high="15" low="0"> <doc>This field has multiple definitions as follows: JUMP - Not Applicable LOOP - The last instruction of the loop. JSR - The last instruction of the subroutine. (Addrss_Range:1K=[9:0];512=[8:0];256=[7:0])</doc> - <use-enum ref="ENUM245" /> + <use-enum ref="ENUM244" /> </bitfield> <bitfield name="PVS_FC_RTN_INST_0" high="31" low="16"> <doc>This field has multiple definitions as follows: JUMP - Not Applicable LOOP - First Instruction of Loop (Typically ACT_ADRS + 1) JSR - First Instruction After JSR (Typically ACT_ADRS + 1). (Addrss_Range:1K=[24:15];512=[23:15];256=[22:15])</doc> - <use-enum ref="ENUM246" /> + <use-enum ref="ENUM245" /> </bitfield> </reg32> </stripe> <stripe offset="0x2290" stride="0x0004" length="16"> <reg32 name="VAP_PVS_FLOW_CNTL_LOOP_INDEX" access="rw" offset="0x0000"> - <doc>Programmable Vertex Shader Flow Control Loop Index Register 0</doc> + <doc>Programmable Vertex Shader Flow Control Loop Index Register 0</doc> <bitfield name="PVS_FC_LOOP_INIT_VAL_0" high="7" low="0"><doc>This field stores the automatic loop index register init value. This is an 8-bit unsigned value 0-255. This field is only used if the corresponding control flow instruction is a loop.</doc></bitfield> <bitfield name="PVS_FC_LOOP_STEP_VAL_0" high="15" low="8"><doc>This field stores the automatic loop index register step value. This is an 8-bit 2`s comp signed value -128-127. This field is only used if the corresponding control flow instruction is a loop.</doc></bitfield> <bitfield name="PVS_FC_LOOP_REPEAT_NO_FLI_0" high="31" low="31"><doc>When this field is set, the automatic loop index register init value is not used at loop activation. The intial loop index is inherited from outer loop. The loop index register step value is used at the end of each loop iteration ; after loop completion, the outer loop index register is restored</doc></bitfield> @@ -5320,42 +5117,15 @@ </reg32> <reg32 name="VAP_VTX_STATE_CNTL" access="rw" offset="0x2180"> <doc>VAP Vertex State Control Register</doc> - <bitfield name="COLOR_0_ASSEMBLY_CNTL" high="1" low="0"> - <doc></doc> - <use-enum ref="ENUM119" /> - </bitfield> - <bitfield name="COLOR_1_ASSEMBLY_CNTL" high="3" low="2"> - <doc></doc> - <use-enum ref="ENUM120" /> - </bitfield> - <bitfield name="COLOR_2_ASSEMBLY_CNTL" high="5" low="4"> - <doc></doc> - <use-enum ref="ENUM121" /> - </bitfield> - <bitfield name="COLOR_3_ASSEMBLY_CNTL" high="7" low="6"> - <doc></doc> - <use-enum ref="ENUM122" /> - </bitfield> - <bitfield name="COLOR_4_ASSEMBLY_CNTL" high="9" low="8"> - <doc></doc> - <use-enum ref="ENUM123" /> - </bitfield> - <bitfield name="COLOR_5_ASSEMBLY_CNTL" high="11" low="10"> - <doc></doc> - <use-enum ref="ENUM124" /> - </bitfield> - <bitfield name="COLOR_6_ASSEMBLY_CNTL" high="13" low="12"> - <doc></doc> - <use-enum ref="ENUM125" /> - </bitfield> - <bitfield name="COLOR_7_ASSEMBLY_CNTL" high="15" low="14"> - <doc></doc> - <use-enum ref="ENUM126" /> - </bitfield> - <bitfield name="UPDATE_USER_COLOR_0_ENA" high="16" low="16"> - <doc></doc> - <use-enum ref="ENUM127" /> - </bitfield> + <bitfield name="COLOR_0_ASSEMBLY_CNTL" high="1" low="0"><use-enum ref="ENUM119" /></bitfield> + <bitfield name="COLOR_1_ASSEMBLY_CNTL" high="3" low="2"><use-enum ref="ENUM120" /></bitfield> + <bitfield name="COLOR_2_ASSEMBLY_CNTL" high="5" low="4"><use-enum ref="ENUM121" /></bitfield> + <bitfield name="COLOR_3_ASSEMBLY_CNTL" high="7" low="6"><use-enum ref="ENUM122" /></bitfield> + <bitfield name="COLOR_4_ASSEMBLY_CNTL" high="9" low="8"><use-enum ref="ENUM123" /></bitfield> + <bitfield name="COLOR_5_ASSEMBLY_CNTL" high="11" low="10"><use-enum ref="ENUM124" /></bitfield> + <bitfield name="COLOR_6_ASSEMBLY_CNTL" high="13" low="12"><use-enum ref="ENUM125" /></bitfield> + <bitfield name="COLOR_7_ASSEMBLY_CNTL" high="15" low="14"><use-enum ref="ENUM126" /></bitfield> + <bitfield name="UPDATE_USER_COLOR_0_ENA" high="16" low="16"><use-enum ref="ENUM127" /></bitfield> <bitfield name="Reserved" high="18" low="18"><doc>Set to 0</doc></bitfield> </reg32> <reg32 name="VAP_VTX_ST_EDGE_FLAGS" access="rw" offset="0x245C"> @@ -5368,14 +5138,8 @@ <doc>Enables hierarchical Z.</doc> <use-enum ref="ENUM5" /> </bitfield> - <bitfield name="HIZ_MIN" high="1" low="1"> - <doc></doc> - <use-enum ref="ENUM129" /> - </bitfield> - <bitfield name="FAST_FILL" high="2" low="2"> - <doc></doc> - <use-enum ref="ENUM5" /> - </bitfield> + <bitfield name="HIZ_MIN" high="1" low="1"><use-enum ref="ENUM129" /></bitfield> + <bitfield name="FAST_FILL" high="2" low="2"><use-enum ref="ENUM5" /></bitfield> <bitfield name="RD_COMP_ENABLE" high="3" low="3"> <doc>Enables reading of compressed Z data from memory to the cache.</doc> <use-enum ref="ENUM5" /> @@ -5386,8 +5150,7 @@ </bitfield> <bitfield name="ZB_CB_CLEAR" high="5" low="5"> <doc>This bit is set when the Z buffer is used to help the CB in clearing a region. Part of the region is cleared by the color buffer and part will be cleared by the Z buffer. Since the Z buffer does not have any write masks in the cache, full micro- tiles need to be written. If a partial micro-tile is touched, then the un-touched part will be unknowns. The cache will operate in write-allocate mode and quads will be accumulated in the cache and then evicted to main memory. The color value is supplied through the ZB_DEPTHCLEARVALUE register.</doc> - <value value="0" name="Z_UNIT_CACHE_CONTROLLER_DOES_RMW"><doc>Z unit cache controller does RMW</doc></value> - <value value="1" name="Z_UNIT_CACHE_CONTROLLER_DOES_CACHE"><doc>Z unit cache controller does cache-line granular Write</doc></value> + <use-enum ref="ENUM130" /> </bitfield> <bitfield name="FORCE_COMPRESSED_STENCIL_V" high="6" low="6"><doc>Enabling this bit will force all the compressed stencil values</doc></bitfield> <bitfield name="ZEQUAL_OPTIMIZE_DISABLE" high="7" low="7"> @@ -5449,10 +5212,7 @@ <value value="0" name="TWOS_COMPLEMENT"><doc>Twos complement</doc></value> <value value="1" name="SIGNED_MAGNITUDE"><doc>Signed magnitude</doc></value> </bitfield> - <bitfield name="STENCIL_REFMASK_FRONT_BACK" high="6" low="6"> - <doc></doc> - <use-enum ref="ENUM5" /> - </bitfield> + <bitfield name="STENCIL_REFMASK_FRONT_BACK" high="6" low="6"><use-enum ref="ENUM5" /></bitfield> </reg32> <reg32 name="ZB_FIFO_SIZE" access="rw" offset="0x4FD0"> <doc>Sets the fifo sizes</doc> @@ -5465,10 +5225,9 @@ <doc>Format of the Data in the Z buffer</doc> <bitfield name="DEPTHFORMAT" high="3" low="0"> <doc>Specifies the format of the Z buffer.</doc> - <use-enum ref="ENUM132" /> + <use-enum ref="ENUM133" /> </bitfield> <bitfield name="INVERT" high="4" low="4"> - <doc></doc> <value value="0" name="IN_13E3_FORMAT"><doc>in 13E3 format , count leading 1`s</doc></value> <value value="1" name="IN_13E3_FORMAT"><doc>in 13E3 format , count leading 0`s.</doc></value> </bitfield> @@ -5502,15 +5261,15 @@ <doc>Z and Stencil Function Control</doc> <bitfield name="ZFUNC" high="2" low="0"> <doc>Specifies the Z function.</doc> - <use-enum ref="ENUM138" /> + <use-enum ref="ENUM139" /> </bitfield> <bitfield name="STENCILFUNC" high="5" low="3"> <doc>Specifies the stencil function.</doc> - <use-enum ref="ENUM139" /> + <use-enum ref="ENUM140" /> </bitfield> <bitfield name="STENCILFAIL" high="8" low="6"> <doc>Specifies the stencil value to be written if the stencil test fails.</doc> - <use-enum ref="ENUM140" /> + <use-enum ref="ENUM141" /> </bitfield> <bitfield name="STENCILZPASS" high="11" low="9"><doc>Same encoding as STENCILFAIL. Specifies the stencil value to be written if the stencil test passes and the Z test passes (or is not enabled).</doc></bitfield> <bitfield name="STENCILZFAIL" high="14" low="12"><doc>Same encoding as STENCILFAIL. Specifies the stencil value to be written if the stencil test passes and the Z test fails.</doc></bitfield> |