~jljusten/mesa - jljusten's mesa repo

Age	Commit message (Expand)	Author	Files	Lines
2023-09-21	intel/isl: Build for Xe2xe2-build-isl	Jordan Justen	3	-1/+9
2023-09-21	intel/genxml: Build with gen20.xml	Jordan Justen	4	-0/+8
2023-09-21	ci/fastboot: Use a case insensitive match for a fastboot line.	Emma Anholt	1	-1/+1
2023-09-21	radeonsi/vcn: Implement destroy_fence vfunc	David Rosca	2	-5/+21
2023-09-21	frontends/va: Destroy fences when destroying surface or context	David Rosca	4	-3/+32
2023-09-21	frontends/va: Track surfaces in context	David Rosca	4	-5/+37
2023-09-21	u_gralloc: Add a function that returns gralloc type	Roman Stratiienko	3	-2/+10
2023-09-21	Revert "util: Add NONNULL macro"	Roman Stratiienko	2	-7/+0
2023-09-21	u_gralloc: Remove usage of NONNULL macro	Roman Stratiienko	2	-20/+18
2023-09-21	u_gralloc: Remove inline modifiers from the functions	Roman Stratiienko	1	-3/+3
2023-09-21	docs: drop outdated and redundant note about the minimum meson version	Eric Engestrom	1	-2/+0
2023-09-21	aco: simplify masked swizzle dpp selection by removing or_mask first	Georg Lehmann	1	-16/+17
2023-09-21	ci: limit build jobs to 30min so that they can retry when they go wrong	Eric Engestrom	1	-0/+8
2023-09-21	rusticl/kernel: skip adding global id offsets if not used	Karol Herbst	1	-21/+22
2023-09-21	rusticl/mesa: fix `set_constant_buffer` when passing an empty buffer	Karol Herbst	1	-1/+1
2023-09-20	intel/fs: Update SSBO & shared uniform block loads for Xe2	Jordan Justen	1	-2/+4
2023-09-20	intel/compiler: Update RT stack_id access for Xe2	Jordan Justen	1	-1/+1
2023-09-20	intel/compiler: Update ray-tracing intrinsic lowering for Xe2	Jordan Justen	1	-9/+11
2023-09-20	intel/compiler: Update lower_trace_ray_logical_send() for Xe2	Jordan Justen	1	-1/+1
2023-09-20	intel/compiler: Update emit_rt_lsc_fence() for Xe2	Jordan Justen	1	-2/+3
2023-09-20	intel/compiler: Update opt_split_sends() for Xe2 reg size	Jordan Justen	1	-1/+1
2023-09-20	intel/compiler/fs: Support Xe2 reg size in assign_curb_setup	Jordan Justen	1	-1/+1
2023-09-20	intel/xe2+: Round up size to reg_unit() in fs_reg_alloc::alloc_spill_reg().	Francisco Jerez	1	-1/+1
2023-09-20	intel/fs/xe2+: Fix calculation of spill message width for Xe2 regs.	Francisco Jerez	1	-3/+4
2023-09-20	intel/fs/xe2+: Fix execution width of SHADER_OPCODE_GET_BUFFER_SIZE for SIMD1...	Francisco Jerez	1	-3/+3
2023-09-20	intel/fs/xe2+: Update regioning lowering offset alignment checks for Xe2 regs.	Francisco Jerez	1	-8/+8
2023-09-20	intel/fs: Lower unsupported regioning with non-trivial 2D regions on FIXED_GRFs.	Francisco Jerez	1	-7/+41
2023-09-20	intel/fs/xe2+: Update TASK/MESH payload setup for Xe2 reg size.	Caio Oliveira	1	-6/+6
2023-09-20	intel/fs/xe2+: Update BS payload setup for Xe2 reg size.	Caio Oliveira	3	-7/+12
2023-09-20	intel/fs/xe2+: Update TES payload setup for Xe2 reg size.	Francisco Jerez	3	-7/+13
2023-09-20	intel/fs/xe2+: Update TCS payload setup for Xe2 reg size.	Francisco Jerez	1	-5/+10
2023-09-20	intel/fs/xe2+: Update GS payload setup for Xe2 reg size.	Francisco Jerez	1	-4/+4
2023-09-20	intel/compiler/xe2: Account for reg_unit() in TES intrinsics	Caio Oliveira	1	-2/+2
2023-09-20	intel/compiler/xe2: Account for reg_unit() in TCS intrinsics	Caio Oliveira	1	-6/+7
2023-09-20	intel/fs/xe2+: Fix payload layout of sampler messages for Xe2 reg size	Francisco Jerez	1	-5/+5
2023-09-20	intel/compiler/xe2: TXD is lowered to SIMD16 in SIMD32 mode	Ian Romanick	1	-2/+4
2023-09-20	intel/compiler/xe2: Use SIMD16 for nir_intrinsic_image_size	Ian Romanick	1	-1/+1
2023-09-20	intel/compiler/xe2: Update fs_visitor::setup_vs_payload to account for Xe2 re...	Ian Romanick	3	-5/+12
2023-09-20	intel/compiler: Adjust barrier emission for Xe2+	Rohan Garg	1	-1/+2
2023-09-20	intel/fs/xe2+: Scale BRW_MAX_MSG_LENGTH by native register size.	Francisco Jerez	1	-1/+1
2023-09-20	intel/compiler: Adjust fence message lengths for new register width on Xe2+	Rohan Garg	1	-2/+2
2023-09-20	intel/compiler: Adjust CS payload registers for new register width on Xe2+	Rohan Garg	1	-1/+2
2023-09-20	intel/fs/xe2+: Round up fs_builder::vgrf() size calculation to HW register unit.	Francisco Jerez	1	-1/+3
2023-09-20	intel/fs/xe2+: Update encoding of FB write message payload.	Francisco Jerez	1	-7/+11
2023-09-20	intel/compiler/xe2+: Represent dispatch_grf_start_reg in native GRF units.	Francisco Jerez	6	-7/+27
2023-09-20	intel/fs/xe2+: Allow increased SIMD width for various get_fpu_lowered_simd_wi...	Francisco Jerez	1	-5/+7
2023-09-20	intel/eu/xe2+: Update validation of GRF region size to account for Xe2 reg size	Francisco Jerez	1	-2/+2
2023-09-20	intel/fs/xe2+: Scale MAX_SAMPLER_MESSAGE_SIZE by native register size.	Francisco Jerez	1	-1/+1
2023-09-20	intel/fs/xe2+: Fixes for increased accumulator register width.	Francisco Jerez	2	-3/+7
2023-09-20	intel/fs/xe2+: Fix grf_count in post-RA scheduling for updated register file ...	Francisco Jerez	1	-1/+1